2066 lines
23 KiB
JSON
2066 lines
23 KiB
JSON
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4,
|
|
2
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffDMAConfig[12].CacheHint",
|
|
[
|
|
100,
|
|
6,
|
|
4
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffDMAConfig[12].PrefetchParticipateEn",
|
|
[
|
|
103,
|
|
4,
|
|
1
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffDMAConfig[13].En",
|
|
[
|
|
104,
|
|
0,
|
|
1
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffDMAConfig[13].CrH",
|
|
[
|
|
104,
|
|
4,
|
|
2
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffDMAConfig[13].CacheHint",
|
|
[
|
|
104,
|
|
6,
|
|
4
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffDMAConfig[13].PrefetchParticipateEn",
|
|
[
|
|
107,
|
|
4,
|
|
1
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffDMAConfig[14].En",
|
|
[
|
|
108,
|
|
0,
|
|
1
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffDMAConfig[14].CrH",
|
|
[
|
|
108,
|
|
4,
|
|
2
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffDMAConfig[14].CacheHint",
|
|
[
|
|
108,
|
|
6,
|
|
4
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffDMAConfig[14].PrefetchParticipateEn",
|
|
[
|
|
111,
|
|
4,
|
|
1
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffDMAConfig[15].En",
|
|
[
|
|
112,
|
|
0,
|
|
1
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffDMAConfig[15].CrH",
|
|
[
|
|
112,
|
|
4,
|
|
2
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffDMAConfig[15].CacheHint",
|
|
[
|
|
112,
|
|
6,
|
|
4
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffDMAConfig[15].PrefetchParticipateEn",
|
|
[
|
|
115,
|
|
4,
|
|
1
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffBaseAddr[0].Addr",
|
|
[
|
|
116,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffBaseAddr[1].Addr",
|
|
[
|
|
120,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffBaseAddr[2].Addr",
|
|
[
|
|
124,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffBaseAddr[3].Addr",
|
|
[
|
|
128,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffBaseAddr[4].Addr",
|
|
[
|
|
132,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffBaseAddr[5].Addr",
|
|
[
|
|
136,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffBaseAddr[6].Addr",
|
|
[
|
|
140,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffBaseAddr[7].Addr",
|
|
[
|
|
144,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffBaseAddr[8].Addr",
|
|
[
|
|
148,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffBaseAddr[9].Addr",
|
|
[
|
|
152,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffBaseAddr[10].Addr",
|
|
[
|
|
156,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffBaseAddr[11].Addr",
|
|
[
|
|
160,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffBaseAddr[12].Addr",
|
|
[
|
|
164,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffBaseAddr[13].Addr",
|
|
[
|
|
168,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffBaseAddr[14].Addr",
|
|
[
|
|
172,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffBaseAddr[15].Addr",
|
|
[
|
|
176,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffBfrSize[0].MemBfrSize",
|
|
[
|
|
180,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffBfrSize[1].MemBfrSize",
|
|
[
|
|
184,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffBfrSize[2].MemBfrSize",
|
|
[
|
|
188,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffBfrSize[3].MemBfrSize",
|
|
[
|
|
192,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffBfrSize[4].MemBfrSize",
|
|
[
|
|
196,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffBfrSize[5].MemBfrSize",
|
|
[
|
|
200,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffBfrSize[6].MemBfrSize",
|
|
[
|
|
204,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffBfrSize[7].MemBfrSize",
|
|
[
|
|
208,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffBfrSize[8].MemBfrSize",
|
|
[
|
|
212,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffBfrSize[9].MemBfrSize",
|
|
[
|
|
216,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffBfrSize[10].MemBfrSize",
|
|
[
|
|
220,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffBfrSize[11].MemBfrSize",
|
|
[
|
|
224,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffBfrSize[12].MemBfrSize",
|
|
[
|
|
228,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffBfrSize[13].MemBfrSize",
|
|
[
|
|
232,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffBfrSize[14].MemBfrSize",
|
|
[
|
|
236,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.KernelDMASrc.CoeffBfrSize[15].MemBfrSize",
|
|
[
|
|
240,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.Common.InDim.Win",
|
|
[
|
|
296,
|
|
0,
|
|
15
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.Common.InDim.Hin",
|
|
[
|
|
298,
|
|
0,
|
|
15
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.Common.ChCfg.InFmt",
|
|
[
|
|
304,
|
|
0,
|
|
2
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.Common.ChCfg.OutFmt",
|
|
[
|
|
304,
|
|
4,
|
|
2
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.Common.Cin.Cin",
|
|
[
|
|
308,
|
|
0,
|
|
17
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.Common.Cout.Cout",
|
|
[
|
|
312,
|
|
0,
|
|
17
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.Common.OutDim.Wout",
|
|
[
|
|
316,
|
|
0,
|
|
15
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.Common.OutDim.Hout",
|
|
[
|
|
318,
|
|
0,
|
|
15
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.Common.ConvCfg.Kw",
|
|
[
|
|
324,
|
|
0,
|
|
5
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.Common.ConvCfg.Kh",
|
|
[
|
|
324,
|
|
5,
|
|
5
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.Common.ConvCfg.OCGSize",
|
|
[
|
|
325,
|
|
2,
|
|
3
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.Common.ConvCfg.Sx",
|
|
[
|
|
325,
|
|
5,
|
|
2
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.Common.ConvCfg.Sy",
|
|
[
|
|
325,
|
|
7,
|
|
2
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.Common.ConvCfg.Px",
|
|
[
|
|
326,
|
|
1,
|
|
5
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.Common.ConvCfg.Py",
|
|
[
|
|
326,
|
|
6,
|
|
5
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.Common.ConvCfg.Ox",
|
|
[
|
|
327,
|
|
4,
|
|
2
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.Common.ConvCfg.Oy",
|
|
[
|
|
327,
|
|
6,
|
|
2
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.Common.GroupConvCfg.NumGroups",
|
|
[
|
|
332,
|
|
0,
|
|
13
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.Common.GroupConvCfg.UnicastEn",
|
|
[
|
|
333,
|
|
6,
|
|
1
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.Common.GroupConvCfg.ElemMultMode",
|
|
[
|
|
333,
|
|
7,
|
|
1
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.Common.GroupConvCfg.UnicastCin",
|
|
[
|
|
334,
|
|
0,
|
|
16
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.Common.TileCfg.TileHeight",
|
|
[
|
|
336,
|
|
0,
|
|
15
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.Common.Cfg.SmallSourceMode",
|
|
[
|
|
348,
|
|
2,
|
|
1
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.Common.Cfg.ShPref",
|
|
[
|
|
349,
|
|
0,
|
|
3
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.Common.Cfg.ShMin",
|
|
[
|
|
349,
|
|
4,
|
|
3
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.Common.Cfg.ShMax",
|
|
[
|
|
350,
|
|
0,
|
|
3
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.Common.Cfg.ActiveNE",
|
|
[
|
|
350,
|
|
3,
|
|
3
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.Common.Cfg.ContextSwitchIn",
|
|
[
|
|
350,
|
|
6,
|
|
1
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.Common.Cfg.ContextSwitchOut",
|
|
[
|
|
351,
|
|
0,
|
|
1
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.Common.Cfg.AccDoubleBufEn",
|
|
[
|
|
351,
|
|
2,
|
|
1
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.Common.TaskInfo.TaskID",
|
|
[
|
|
352,
|
|
0,
|
|
16
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.Common.TaskInfo.TaskQ",
|
|
[
|
|
354,
|
|
0,
|
|
4
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.Common.TaskInfo.NID",
|
|
[
|
|
354,
|
|
4,
|
|
8
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.Common.DPE.Category",
|
|
[
|
|
356,
|
|
0,
|
|
4
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.TileDMASrc.DMAConfig.En",
|
|
[
|
|
364,
|
|
0,
|
|
1
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.TileDMASrc.DMAConfig.CrH",
|
|
[
|
|
364,
|
|
4,
|
|
2
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.TileDMASrc.DMAConfig.CacheHint",
|
|
[
|
|
364,
|
|
6,
|
|
4
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.TileDMASrc.DMAConfig.CacheHintReuse",
|
|
[
|
|
365,
|
|
2,
|
|
4
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.TileDMASrc.DMAConfig.CacheHintNoReuse",
|
|
[
|
|
365,
|
|
6,
|
|
4
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.TileDMASrc.DMAConfig.DependencyMode",
|
|
[
|
|
366,
|
|
2,
|
|
2
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.TileDMASrc.BaseAddr.Addr",
|
|
[
|
|
372,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.TileDMASrc.RowStride.Stride",
|
|
[
|
|
376,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.TileDMASrc.PlaneStride.PlaneStride",
|
|
[
|
|
380,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.TileDMASrc.DepthStride.Stride",
|
|
[
|
|
384,
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26
|
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|
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|
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[
|
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"aneRegs.TileDMASrc.GroupStride.Stride",
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26
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2
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"aneRegs.TileDMASrc.Fmt.Shift",
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[
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1
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|
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[
|
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[
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2
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|
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"aneRegs.TileDMASrc.Fmt.OffsetCh",
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[
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3
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]
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|
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[
|
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"aneRegs.TileDMASrc.Fmt.Interleave",
|
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[
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4
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"aneRegs.TileDMASrc.Fmt.CmpVec",
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4
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[
|
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"aneRegs.TileDMASrc.PixelOffset[0].Offset",
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[
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16
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|
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|
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[
|
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"aneRegs.TileDMASrc.PixelOffset[1].Offset",
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[
|
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448,
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16
|
|
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|
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|
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[
|
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"aneRegs.TileDMASrc.PixelOffset[2].Offset",
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[
|
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452,
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16
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|
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|
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|
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[
|
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"aneRegs.TileDMASrc.PixelOffset[3].Offset",
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[
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456,
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0,
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16
|
|
]
|
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|
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[
|
|
"aneRegs.L2.L2Cfg.InputReLU",
|
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[
|
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480,
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0,
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1
|
|
]
|
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|
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[
|
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"aneRegs.L2.L2Cfg.PaddingMode",
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[
|
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480,
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2,
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2
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|
]
|
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],
|
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[
|
|
"aneRegs.L2.SourceCfg.SourceType",
|
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[
|
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484,
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0,
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2
|
|
]
|
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],
|
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[
|
|
"aneRegs.L2.SourceCfg.Dependent",
|
|
[
|
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484,
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2,
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2
|
|
]
|
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],
|
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[
|
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"aneRegs.L2.SourceCfg.AliasConvSrc",
|
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[
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484,
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4,
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1
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]
|
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|
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[
|
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"aneRegs.L2.SourceCfg.AliasConvRslt",
|
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[
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|
484,
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5,
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1
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]
|
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|
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[
|
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"aneRegs.L2.SourceCfg.DMAFmt",
|
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[
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|
484,
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6,
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2
|
|
]
|
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],
|
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[
|
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"aneRegs.L2.SourceCfg.DMAInterleave",
|
|
[
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|
485,
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0,
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4
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|
]
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|
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[
|
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"aneRegs.L2.SourceCfg.DMACmpVec",
|
|
[
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|
485,
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4,
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|
4
|
|
]
|
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],
|
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[
|
|
"aneRegs.L2.SourceCfg.DMAOffsetCh",
|
|
[
|
|
486,
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|
0,
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|
3
|
|
]
|
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],
|
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[
|
|
"aneRegs.L2.SourceCfg.AliasPlanarSrc",
|
|
[
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|
486,
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4,
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1
|
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]
|
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],
|
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[
|
|
"aneRegs.L2.SourceCfg.AliasPlanarRslt",
|
|
[
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|
486,
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6,
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|
1
|
|
]
|
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],
|
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[
|
|
"aneRegs.L2.SourceBase.Addr",
|
|
[
|
|
488,
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|
4,
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|
17
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.L2.SourceChannelStride.Stride",
|
|
[
|
|
492,
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|
4,
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|
17
|
|
]
|
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],
|
|
[
|
|
"aneRegs.L2.SourceRowStride.Stride",
|
|
[
|
|
496,
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|
4,
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|
17
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.L2.ResultCfg.ResultType",
|
|
[
|
|
528,
|
|
0,
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|
2
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.L2.ResultCfg.L2BfrMode",
|
|
[
|
|
528,
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|
3,
|
|
1
|
|
]
|
|
],
|
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[
|
|
"aneRegs.L2.ResultCfg.AliasConvSrc",
|
|
[
|
|
528,
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|
4,
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|
1
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.L2.ResultCfg.AliasConvRslt",
|
|
[
|
|
528,
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|
5,
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|
1
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.L2.ResultCfg.DMAFmt",
|
|
[
|
|
528,
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|
6,
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|
2
|
|
]
|
|
],
|
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[
|
|
"aneRegs.L2.ResultCfg.DMAInterleave",
|
|
[
|
|
529,
|
|
0,
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|
4
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.L2.ResultCfg.DMACmpVec",
|
|
[
|
|
529,
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|
4,
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|
4
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.L2.ResultCfg.DMAOffsetCh",
|
|
[
|
|
530,
|
|
0,
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|
3
|
|
]
|
|
],
|
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[
|
|
"aneRegs.L2.ResultCfg.AliasPlanarSrc",
|
|
[
|
|
530,
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|
4,
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|
1
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.L2.ResultCfg.AliasPlanarRslt",
|
|
[
|
|
530,
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|
6,
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|
1
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.L2.ResultBase.Addr",
|
|
[
|
|
532,
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|
4,
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|
17
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.L2.ConvResultChannelStride.Stride",
|
|
[
|
|
536,
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|
4,
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|
17
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.L2.ConvResultRowStride.Stride",
|
|
[
|
|
540,
|
|
4,
|
|
17
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.NE.KernelCfg.KernelFmt",
|
|
[
|
|
576,
|
|
0,
|
|
2
|
|
]
|
|
],
|
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[
|
|
"aneRegs.NE.KernelCfg.PalettizedEn",
|
|
[
|
|
576,
|
|
2,
|
|
1
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.NE.KernelCfg.PalettizedBits",
|
|
[
|
|
576,
|
|
4,
|
|
4
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.NE.KernelCfg.SparseFmt",
|
|
[
|
|
577,
|
|
0,
|
|
1
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.NE.KernelCfg.GroupKernelReuse",
|
|
[
|
|
577,
|
|
2,
|
|
1
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.NE.MACCfg.OpMode",
|
|
[
|
|
580,
|
|
0,
|
|
3
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.NE.MACCfg.KernelMode",
|
|
[
|
|
580,
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|
3,
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|
1
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.NE.MACCfg.BiasMode",
|
|
[
|
|
580,
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|
4,
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|
1
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.NE.MACCfg.MatrixBiasEn",
|
|
[
|
|
580,
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|
6,
|
|
1
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.NE.MACCfg.BinaryPoint",
|
|
[
|
|
581,
|
|
0,
|
|
5
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.NE.MACCfg.PostScaleMode",
|
|
[
|
|
581,
|
|
6,
|
|
1
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.NE.MACCfg.NonlinearMode",
|
|
[
|
|
582,
|
|
0,
|
|
2
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.NE.MatrixVectorBias.MatrixVectorBias",
|
|
[
|
|
584,
|
|
0,
|
|
16
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.NE.AccBias.AccBias",
|
|
[
|
|
588,
|
|
0,
|
|
16
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.NE.AccBias.AccBiasShift",
|
|
[
|
|
590,
|
|
0,
|
|
5
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.NE.PostScale.PostScale",
|
|
[
|
|
592,
|
|
0,
|
|
16
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.NE.PostScale.PostRightShift",
|
|
[
|
|
594,
|
|
0,
|
|
5
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.TileDMADst.DMAConfig.En",
|
|
[
|
|
600,
|
|
0,
|
|
1
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.TileDMADst.DMAConfig.CrH",
|
|
[
|
|
600,
|
|
4,
|
|
2
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.TileDMADst.DMAConfig.CacheHint",
|
|
[
|
|
600,
|
|
6,
|
|
4
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.TileDMADst.DMAConfig.L2BfrMode",
|
|
[
|
|
603,
|
|
2,
|
|
1
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.TileDMADst.DMAConfig.BypassEOW",
|
|
[
|
|
603,
|
|
3,
|
|
1
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.TileDMADst.BaseAddr.Addr",
|
|
[
|
|
604,
|
|
6,
|
|
26
|
|
]
|
|
],
|
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[
|
|
"aneRegs.TileDMADst.RowStride.RowStride",
|
|
[
|
|
608,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.TileDMADst.PlaneStride.PlaneStride",
|
|
[
|
|
612,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.TileDMADst.DepthStride.DepthStride",
|
|
[
|
|
616,
|
|
6,
|
|
26
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.TileDMADst.GroupStride.GroupStride",
|
|
[
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|
620,
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|
6,
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|
26
|
|
]
|
|
],
|
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[
|
|
"aneRegs.TileDMADst.Fmt.FmtMode",
|
|
[
|
|
624,
|
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0,
|
|
2
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.TileDMADst.Fmt.Truncate",
|
|
[
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|
624,
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|
4,
|
|
2
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.TileDMADst.Fmt.Shift",
|
|
[
|
|
625,
|
|
0,
|
|
1
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.TileDMADst.Fmt.MemFmt",
|
|
[
|
|
625,
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|
4,
|
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2
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.TileDMADst.Fmt.OffsetCh",
|
|
[
|
|
626,
|
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0,
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|
3
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.TileDMADst.Fmt.ZeroPadLast",
|
|
[
|
|
626,
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|
4,
|
|
1
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.TileDMADst.Fmt.ZeroPadFirst",
|
|
[
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|
626,
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|
5,
|
|
1
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.TileDMADst.Fmt.CmpVecFill",
|
|
[
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|
626,
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|
6,
|
|
1
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.TileDMADst.Fmt.Interleave",
|
|
[
|
|
627,
|
|
0,
|
|
4
|
|
]
|
|
],
|
|
[
|
|
"aneRegs.TileDMADst.Fmt.CmpVec",
|
|
[
|
|
627,
|
|
4,
|
|
4
|
|
]
|
|
]
|
|
] |