81 lines
2.4 KiB
ArmAsm
81 lines
2.4 KiB
ArmAsm
.global _start
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_start:
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.rodata
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.align 0x10
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.global code.kd
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.type code.kd,STT_OBJECT
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# amd_kernel_code_t (must be at 0x440 for kernel_code_entry_byte_offset to be right)
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code.kd:
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# amd_kernel_..., amd_machine_...
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.long 0,0,0,0
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# kernel_code_entry_byte_offset, kernel_code_prefetch_byte_offset
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.long 0x00000bc0,0x00000000,0x00000000,0x00000000
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# kernel_code_prefetch_byte_size, max_scratch_backing_memory_byte_size
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.long 0,0,0,0
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# compute_pgm_rsrc1, compute_pgm_rsrc2, kernel_code_properties, workitem_private_segment_byte_size
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.long 0x60af0000,0x0000009e,0x00000408,0x00000000
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# compute_pgm_rsrc1 |= AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_32 | AMD_COMPUTE_PGM_RSRC_ONE_FLOAT_DENORM_MODE_16_64
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# compute_pgm_rsrc1 |= AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_DX10_CLAMP | AMD_COMPUTE_PGM_RSRC_ONE_ENABLE_IEEE_MODE
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# compute_pgm_rsrc2 |= AMD_COMPUTE_PGM_RSRC_TWO_USER_SGPR_COUNT = 0xF
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# compute_pgm_rsrc2 |= AMD_COMPUTE_PGM_RSRC_TWO_ENABLE_SGPR_WORKGROUP_ID_X
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# kernel_code_properties |= AMD_KERNEL_CODE_PROPERTIES_ENABLE_SGPR_KERNARG_SEGMENT_PTR = 1
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# kernel_code_properties |= AMD_KERNEL_CODE_PROPERTIES_RESERVED1 = 1
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.text
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.global code
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.type code,STT_FUNC
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code:
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# https://llvm.org/docs/AMDGPUUsage.html#initial-kernel-execution-state
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# s[0:1] contains the kernarg_address
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# TODO: can we use s[2:3] if this was really a wave since we only alloced 2 SGPRs?
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s_load_b64 s[2:3], s[0:1], null
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s_mov_b32 s8, 0
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loop:
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s_addk_i32 s8, 1
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s_cmp_eq_u32 s8, 100000
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// FLOPS
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s_cbranch_scc0 loop
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# wait for the s_load_b64
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s_waitcnt lgkmcnt(0)
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v_dual_mov_b32 v0, 4 :: v_dual_mov_b32 v1, 2.0
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global_store_b32 v0, v1, s[2:3]
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# Deallocate all VGPRs for this wave. Use only when next instruction is S_ENDPGM.
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s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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s_endpgm
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s_code_end
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.amdgpu_metadata
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amdhsa.kernels:
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- .args:
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- .address_space: global
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.name: a
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.offset: 0
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.size: 8
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.type_name: 'float*'
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.value_kind: global_buffer
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.group_segment_fixed_size: 0
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.kernarg_segment_align: 8
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.kernarg_segment_size: 8
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.language: OpenCL C
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.language_version:
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- 1
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- 2
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.max_flat_workgroup_size: 256
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.name: code
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.private_segment_fixed_size: 0
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.sgpr_count: 2
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.sgpr_spill_count: 0
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.symbol: code.kd
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.uses_dynamic_stack: false
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.vgpr_count: 256
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.vgpr_spill_count: 0
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.wavefront_size: 32
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amdhsa.target: amdgcn-amd-amdhsa--gfx1100
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amdhsa.version:
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- 1
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- 2
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.end_amdgpu_metadata
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