348 lines
9.1 KiB
C
348 lines
9.1 KiB
C
/*
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* Copyright 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __AMDGPU_SMU_H__
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#define __AMDGPU_SMU_H__
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#define int32_t int
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#define uint32_t unsigned int
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#define int8_t signed char
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#define uint8_t unsigned char
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#define uint16_t unsigned short
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#define int16_t short
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#define uint64_t unsigned long long
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#define bool _Bool
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#define u32 unsigned int
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#define SMU_THERMAL_MINIMUM_ALERT_TEMP 0
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#define SMU_THERMAL_MAXIMUM_ALERT_TEMP 255
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#define SMU_TEMPERATURE_UNITS_PER_CENTIGRADES 1000
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#define SMU_FW_NAME_LEN 0x24
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#define SMU_DPM_USER_PROFILE_RESTORE (1 << 0)
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#define SMU_CUSTOM_FAN_SPEED_RPM (1 << 1)
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#define SMU_CUSTOM_FAN_SPEED_PWM (1 << 2)
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// Power Throttlers
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#define SMU_THROTTLER_PPT0_BIT 0
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#define SMU_THROTTLER_PPT1_BIT 1
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#define SMU_THROTTLER_PPT2_BIT 2
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#define SMU_THROTTLER_PPT3_BIT 3
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#define SMU_THROTTLER_SPL_BIT 4
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#define SMU_THROTTLER_FPPT_BIT 5
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#define SMU_THROTTLER_SPPT_BIT 6
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#define SMU_THROTTLER_SPPT_APU_BIT 7
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// Current Throttlers
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#define SMU_THROTTLER_TDC_GFX_BIT 16
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#define SMU_THROTTLER_TDC_SOC_BIT 17
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#define SMU_THROTTLER_TDC_MEM_BIT 18
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#define SMU_THROTTLER_TDC_VDD_BIT 19
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#define SMU_THROTTLER_TDC_CVIP_BIT 20
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#define SMU_THROTTLER_EDC_CPU_BIT 21
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#define SMU_THROTTLER_EDC_GFX_BIT 22
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#define SMU_THROTTLER_APCC_BIT 23
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// Temperature
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#define SMU_THROTTLER_TEMP_GPU_BIT 32
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#define SMU_THROTTLER_TEMP_CORE_BIT 33
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#define SMU_THROTTLER_TEMP_MEM_BIT 34
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#define SMU_THROTTLER_TEMP_EDGE_BIT 35
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#define SMU_THROTTLER_TEMP_HOTSPOT_BIT 36
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#define SMU_THROTTLER_TEMP_SOC_BIT 37
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#define SMU_THROTTLER_TEMP_VR_GFX_BIT 38
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#define SMU_THROTTLER_TEMP_VR_SOC_BIT 39
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#define SMU_THROTTLER_TEMP_VR_MEM0_BIT 40
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#define SMU_THROTTLER_TEMP_VR_MEM1_BIT 41
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#define SMU_THROTTLER_TEMP_LIQUID0_BIT 42
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#define SMU_THROTTLER_TEMP_LIQUID1_BIT 43
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#define SMU_THROTTLER_VRHOT0_BIT 44
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#define SMU_THROTTLER_VRHOT1_BIT 45
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#define SMU_THROTTLER_PROCHOT_CPU_BIT 46
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#define SMU_THROTTLER_PROCHOT_GFX_BIT 47
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// Other
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#define SMU_THROTTLER_PPM_BIT 56
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#define SMU_THROTTLER_FIT_BIT 57
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struct smu_hw_power_state {
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unsigned int magic;
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};
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struct smu_power_state;
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enum smu_state_ui_label {
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SMU_STATE_UI_LABEL_NONE,
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SMU_STATE_UI_LABEL_BATTERY,
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SMU_STATE_UI_TABEL_MIDDLE_LOW,
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SMU_STATE_UI_LABEL_BALLANCED,
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SMU_STATE_UI_LABEL_MIDDLE_HIGHT,
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SMU_STATE_UI_LABEL_PERFORMANCE,
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SMU_STATE_UI_LABEL_BACO,
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};
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enum smu_state_classification_flag {
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SMU_STATE_CLASSIFICATION_FLAG_BOOT = 0x0001,
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SMU_STATE_CLASSIFICATION_FLAG_THERMAL = 0x0002,
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SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE = 0x0004,
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SMU_STATE_CLASSIFICATION_FLAG_RESET = 0x0008,
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SMU_STATE_CLASSIFICATION_FLAG_FORCED = 0x0010,
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SMU_STATE_CLASSIFICATION_FLAG_USER_3D_PERFORMANCE = 0x0020,
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SMU_STATE_CLASSIFICATION_FLAG_USER_2D_PERFORMANCE = 0x0040,
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SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE = 0x0080,
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SMU_STATE_CLASSIFICATION_FLAG_AC_OVERDIRVER_TEMPLATE = 0x0100,
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SMU_STATE_CLASSIFICATION_FLAG_UVD = 0x0200,
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SMU_STATE_CLASSIFICATION_FLAG_3D_PERFORMANCE_LOW = 0x0400,
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SMU_STATE_CLASSIFICATION_FLAG_ACPI = 0x0800,
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SMU_STATE_CLASSIFICATION_FLAG_HD2 = 0x1000,
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SMU_STATE_CLASSIFICATION_FLAG_UVD_HD = 0x2000,
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SMU_STATE_CLASSIFICATION_FLAG_UVD_SD = 0x4000,
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SMU_STATE_CLASSIFICATION_FLAG_USER_DC_PERFORMANCE = 0x8000,
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SMU_STATE_CLASSIFICATION_FLAG_DC_OVERDIRVER_TEMPLATE = 0x10000,
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SMU_STATE_CLASSIFICATION_FLAG_BACO = 0x20000,
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SMU_STATE_CLASSIFICATIN_FLAG_LIMITED_POWER_SOURCE2 = 0x40000,
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SMU_STATE_CLASSIFICATION_FLAG_ULV = 0x80000,
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SMU_STATE_CLASSIFICATION_FLAG_UVD_MVC = 0x100000,
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};
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struct smu_state_classification_block {
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enum smu_state_ui_label ui_label;
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enum smu_state_classification_flag flags;
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int bios_index;
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bool temporary_state;
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bool to_be_deleted;
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};
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struct smu_state_pcie_block {
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unsigned int lanes;
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};
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enum smu_refreshrate_source {
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SMU_REFRESHRATE_SOURCE_EDID,
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SMU_REFRESHRATE_SOURCE_EXPLICIT
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};
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struct smu_state_display_block {
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bool disable_frame_modulation;
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bool limit_refreshrate;
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enum smu_refreshrate_source refreshrate_source;
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int explicit_refreshrate;
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int edid_refreshrate_index;
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bool enable_vari_bright;
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};
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struct smu_state_memory_block {
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bool dll_off;
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uint8_t m3arb;
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uint8_t unused[3];
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};
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struct smu_state_software_algorithm_block {
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bool disable_load_balancing;
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bool enable_sleep_for_timestamps;
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};
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struct smu_temperature_range {
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int min;
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int max;
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int edge_emergency_max;
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int hotspot_min;
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int hotspot_crit_max;
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int hotspot_emergency_max;
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int mem_min;
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int mem_crit_max;
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int mem_emergency_max;
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int software_shutdown_temp;
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int software_shutdown_temp_offset;
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};
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struct smu_state_validation_block {
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bool single_display_only;
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bool disallow_on_dc;
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uint8_t supported_power_levels;
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};
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struct smu_uvd_clocks {
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uint32_t vclk;
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uint32_t dclk;
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};
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/**
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* Structure to hold a SMU Power State.
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*/
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enum smu_power_src_type {
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SMU_POWER_SOURCE_AC,
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SMU_POWER_SOURCE_DC,
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SMU_POWER_SOURCE_COUNT,
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};
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enum smu_ppt_limit_type {
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SMU_DEFAULT_PPT_LIMIT = 0,
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SMU_FAST_PPT_LIMIT,
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};
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enum smu_ppt_limit_level {
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SMU_PPT_LIMIT_MIN = -1,
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SMU_PPT_LIMIT_CURRENT,
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SMU_PPT_LIMIT_DEFAULT,
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SMU_PPT_LIMIT_MAX,
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};
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enum smu_memory_pool_size {
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SMU_MEMORY_POOL_SIZE_ZERO = 0,
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SMU_MEMORY_POOL_SIZE_256_MB = 0x10000000,
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SMU_MEMORY_POOL_SIZE_512_MB = 0x20000000,
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SMU_MEMORY_POOL_SIZE_1_GB = 0x40000000,
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SMU_MEMORY_POOL_SIZE_2_GB = 0x80000000,
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};
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enum smu_clk_type {
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SMU_GFXCLK,
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SMU_VCLK,
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SMU_DCLK,
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SMU_VCLK1,
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SMU_DCLK1,
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SMU_ECLK,
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SMU_SOCCLK,
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SMU_UCLK,
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SMU_DCEFCLK,
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SMU_DISPCLK,
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SMU_PIXCLK,
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SMU_PHYCLK,
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SMU_FCLK,
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SMU_SCLK,
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SMU_MCLK,
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SMU_PCIE,
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SMU_LCLK,
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SMU_OD_CCLK,
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SMU_OD_SCLK,
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SMU_OD_MCLK,
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SMU_OD_VDDC_CURVE,
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SMU_OD_RANGE,
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SMU_OD_VDDGFX_OFFSET,
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SMU_OD_FAN_CURVE,
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SMU_OD_ACOUSTIC_LIMIT,
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SMU_OD_ACOUSTIC_TARGET,
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SMU_OD_FAN_TARGET_TEMPERATURE,
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SMU_OD_FAN_MINIMUM_PWM,
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SMU_CLK_COUNT,
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};
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struct smu_user_dpm_profile {
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uint32_t fan_mode;
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uint32_t power_limit;
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uint32_t fan_speed_pwm;
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uint32_t fan_speed_rpm;
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uint32_t flags;
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uint32_t user_od;
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/* user clock state information */
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uint32_t clk_mask[SMU_CLK_COUNT];
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uint32_t clk_dependency;
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};
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#define SMU_TABLE_INIT(tables, table_id, s, a, d) \
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do { \
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tables[table_id].size = s; \
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tables[table_id].align = a; \
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tables[table_id].domain = d; \
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} while (0)
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struct smu_table {
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uint64_t size;
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uint32_t align;
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uint8_t domain;
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uint64_t mc_address;
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void *cpu_addr;
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struct amdgpu_bo *bo;
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uint32_t version;
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};
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enum smu_perf_level_designation {
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PERF_LEVEL_ACTIVITY,
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PERF_LEVEL_POWER_CONTAINMENT,
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};
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struct smu_performance_level {
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uint32_t core_clock;
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uint32_t memory_clock;
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uint32_t vddc;
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uint32_t vddci;
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uint32_t non_local_mem_freq;
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uint32_t non_local_mem_width;
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};
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struct smu_clock_info {
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uint32_t min_mem_clk;
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uint32_t max_mem_clk;
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uint32_t min_eng_clk;
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uint32_t max_eng_clk;
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uint32_t min_bus_bandwidth;
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uint32_t max_bus_bandwidth;
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};
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struct smu_bios_boot_up_values {
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uint32_t revision;
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uint32_t gfxclk;
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uint32_t uclk;
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uint32_t socclk;
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uint32_t dcefclk;
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uint32_t eclk;
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uint32_t vclk;
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uint32_t dclk;
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uint16_t vddc;
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uint16_t vddci;
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uint16_t mvddc;
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uint16_t vdd_gfx;
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uint8_t cooling_id;
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uint32_t pp_table_id;
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uint32_t format_revision;
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uint32_t content_revision;
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uint32_t fclk;
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uint32_t lclk;
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uint32_t firmware_caps;
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};
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enum smu_table_id {
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SMU_TABLE_PPTABLE = 0,
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SMU_TABLE_WATERMARKS,
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SMU_TABLE_CUSTOM_DPM,
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SMU_TABLE_DPMCLOCKS,
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SMU_TABLE_AVFS,
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SMU_TABLE_AVFS_PSM_DEBUG,
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SMU_TABLE_AVFS_FUSE_OVERRIDE,
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SMU_TABLE_PMSTATUSLOG,
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SMU_TABLE_SMU_METRICS,
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SMU_TABLE_DRIVER_SMU_CONFIG,
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SMU_TABLE_ACTIVITY_MONITOR_COEFF,
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SMU_TABLE_OVERDRIVE,
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SMU_TABLE_I2C_COMMANDS,
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SMU_TABLE_PACE,
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SMU_TABLE_ECCINFO,
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SMU_TABLE_COMBO_PPTABLE,
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SMU_TABLE_WIFIBAND,
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SMU_TABLE_COUNT,
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};
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#endif
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