107 lines
3.0 KiB
C
107 lines
3.0 KiB
C
static void uart_rx_ring(uart_ring *q){
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// Do not read out directly if DMA enabled
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ENTER_CRITICAL();
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// Read out RX buffer
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uint8_t c = q->uart->RDR; // This read after reading SR clears a bunch of interrupts
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uint16_t next_w_ptr = (q->w_ptr_rx + 1U) % q->rx_fifo_size;
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if ((next_w_ptr == q->r_ptr_rx) && q->overwrite) {
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// overwrite mode: drop oldest byte
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q->r_ptr_rx = (q->r_ptr_rx + 1U) % q->rx_fifo_size;
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}
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// Do not overwrite buffer data
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if (next_w_ptr != q->r_ptr_rx) {
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q->elems_rx[q->w_ptr_rx] = c;
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q->w_ptr_rx = next_w_ptr;
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if (q->callback != NULL) {
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q->callback(q);
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}
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}
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EXIT_CRITICAL();
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}
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void uart_tx_ring(uart_ring *q){
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ENTER_CRITICAL();
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// Send out next byte of TX buffer
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if (q->w_ptr_tx != q->r_ptr_tx) {
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// Only send if transmit register is empty (aka last byte has been sent)
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if ((q->uart->ISR & USART_ISR_TXE_TXFNF) != 0U) {
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q->uart->TDR = q->elems_tx[q->r_ptr_tx]; // This clears TXE
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q->r_ptr_tx = (q->r_ptr_tx + 1U) % q->tx_fifo_size;
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}
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// Enable TXE interrupt if there is still data to be sent
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if(q->r_ptr_tx != q->w_ptr_tx){
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q->uart->CR1 |= USART_CR1_TXEIE;
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} else {
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q->uart->CR1 &= ~USART_CR1_TXEIE;
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}
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}
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EXIT_CRITICAL();
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}
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void uart_set_baud(USART_TypeDef *u, unsigned int baud) {
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// UART7 is connected to APB1 at 60MHz
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u->BRR = 60000000U / baud;
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}
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// This read after reading ISR clears all error interrupts. We don't want compiler warnings, nor optimizations
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#define UART_READ_RDR(uart) volatile uint8_t t = (uart)->RDR; UNUSED(t);
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static void uart_interrupt_handler(uart_ring *q) {
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ENTER_CRITICAL();
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// Read UART status. This is also the first step necessary in clearing most interrupts
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uint32_t status = q->uart->ISR;
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// If RXFNE is set, perform a read. This clears RXFNE, ORE, IDLE, NF and FE
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if((status & USART_ISR_RXNE_RXFNE) != 0U){
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uart_rx_ring(q);
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}
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// Detect errors and clear them
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uint32_t err = (status & USART_ISR_ORE) | (status & USART_ISR_NE) | (status & USART_ISR_FE) | (status & USART_ISR_PE);
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if(err != 0U){
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#ifdef DEBUG_UART
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print("Encountered UART error: "); puth(err); print("\n");
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#endif
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UART_READ_RDR(q->uart)
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}
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if ((err & USART_ISR_ORE) != 0U) {
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q->uart->ICR |= USART_ICR_ORECF;
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} else if ((err & USART_ISR_NE) != 0U) {
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q->uart->ICR |= USART_ICR_NECF;
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} else if ((err & USART_ISR_FE) != 0U) {
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q->uart->ICR |= USART_ICR_FECF;
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} else if ((err & USART_ISR_PE) != 0U) {
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q->uart->ICR |= USART_ICR_PECF;
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} else {}
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// Send if necessary
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uart_tx_ring(q);
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EXIT_CRITICAL();
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}
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static void UART7_IRQ_Handler(void) { uart_interrupt_handler(&uart_ring_som_debug); }
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void uart_init(uart_ring *q, int baud) {
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if (q->uart == UART7) {
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REGISTER_INTERRUPT(UART7_IRQn, UART7_IRQ_Handler, 150000U, FAULT_INTERRUPT_RATE_UART_7)
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uart_set_baud(q->uart, baud);
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q->uart->CR1 = USART_CR1_UE | USART_CR1_TE | USART_CR1_RE;
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// Enable interrupt on RX not empty
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q->uart->CR1 |= USART_CR1_RXNEIE;
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// Enable UART interrupts
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NVIC_EnableIRQ(UART7_IRQn);
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}
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}
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