228 lines
7.5 KiB
C
228 lines
7.5 KiB
C
#include "llfdcan_declarations.h"
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// kbps multiplied by 10
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const uint32_t speeds[SPEEDS_ARRAY_SIZE] = {100U, 200U, 500U, 1000U, 1250U, 2500U, 5000U, 10000U};
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const uint32_t data_speeds[DATA_SPEEDS_ARRAY_SIZE] = {100U, 200U, 500U, 1000U, 1250U, 2500U, 5000U, 10000U, 20000U, 50000U};
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static bool fdcan_request_init(FDCAN_GlobalTypeDef *FDCANx) {
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bool ret = true;
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// Exit from sleep mode
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FDCANx->CCCR &= ~(FDCAN_CCCR_CSR);
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while ((FDCANx->CCCR & FDCAN_CCCR_CSA) == FDCAN_CCCR_CSA);
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// Request init
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uint32_t timeout_counter = 0U;
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FDCANx->CCCR |= FDCAN_CCCR_INIT;
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while ((FDCANx->CCCR & FDCAN_CCCR_INIT) == 0U) {
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// Delay for about 1ms
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delay(10000);
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timeout_counter++;
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if (timeout_counter >= CAN_INIT_TIMEOUT_MS){
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ret = false;
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break;
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}
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}
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return ret;
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}
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static bool fdcan_exit_init(FDCAN_GlobalTypeDef *FDCANx) {
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bool ret = true;
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FDCANx->CCCR &= ~(FDCAN_CCCR_INIT);
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uint32_t timeout_counter = 0U;
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while ((FDCANx->CCCR & FDCAN_CCCR_INIT) != 0U) {
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// Delay for about 1ms
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delay(10000);
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timeout_counter++;
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if (timeout_counter >= CAN_INIT_TIMEOUT_MS) {
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ret = false;
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break;
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}
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}
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return ret;
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}
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bool llcan_set_speed(FDCAN_GlobalTypeDef *FDCANx, uint32_t speed, uint32_t data_speed, bool non_iso, bool loopback, bool silent) {
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UNUSED(speed);
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bool ret = fdcan_request_init(FDCANx);
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if (ret) {
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// Enable config change
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FDCANx->CCCR |= FDCAN_CCCR_CCE;
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//Reset operation mode to Normal
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FDCANx->CCCR &= ~(FDCAN_CCCR_TEST);
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FDCANx->TEST &= ~(FDCAN_TEST_LBCK);
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FDCANx->CCCR &= ~(FDCAN_CCCR_MON);
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FDCANx->CCCR &= ~(FDCAN_CCCR_ASM);
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FDCANx->CCCR &= ~(FDCAN_CCCR_NISO);
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// TODO: add as a separate safety mode
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// Enable ASM restricted operation(for debug or automatic bitrate switching)
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//FDCANx->CCCR |= FDCAN_CCCR_ASM;
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uint8_t prescaler = BITRATE_PRESCALER;
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if (speed < 2500U) {
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// The only way to support speeds lower than 250Kbit/s (down to 10Kbit/s)
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prescaler = BITRATE_PRESCALER * 16U;
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}
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// Set the nominal bit timing values
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uint32_t tq = CAN_QUANTA(speed, prescaler);
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uint32_t sp = CAN_SP_NOMINAL;
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uint32_t seg1 = CAN_SEG1(tq, sp);
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uint32_t seg2 = CAN_SEG2(tq, sp);
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uint8_t sjw = MIN(127U, seg2);
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FDCANx->NBTP = (((sjw & 0x7FUL)-1U)<<FDCAN_NBTP_NSJW_Pos) | (((seg1 & 0xFFU)-1U)<<FDCAN_NBTP_NTSEG1_Pos) | (((seg2 & 0x7FU)-1U)<<FDCAN_NBTP_NTSEG2_Pos) | (((prescaler & 0x1FFUL)-1U)<<FDCAN_NBTP_NBRP_Pos);
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// Set the data bit timing values
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if (data_speed == 50000U) {
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sp = CAN_SP_DATA_5M;
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} else {
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sp = CAN_SP_DATA_2M;
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}
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tq = CAN_QUANTA(data_speed, prescaler);
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seg1 = CAN_SEG1(tq, sp);
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seg2 = CAN_SEG2(tq, sp);
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sjw = MIN(15U, seg2);
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FDCANx->DBTP = (((sjw & 0xFUL)-1U)<<FDCAN_DBTP_DSJW_Pos) | (((seg1 & 0x1FU)-1U)<<FDCAN_DBTP_DTSEG1_Pos) | (((seg2 & 0xFU)-1U)<<FDCAN_DBTP_DTSEG2_Pos) | (((prescaler & 0x1FUL)-1U)<<FDCAN_DBTP_DBRP_Pos);
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if (non_iso) {
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// FD non-ISO mode
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FDCANx->CCCR |= FDCAN_CCCR_NISO;
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}
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// Silent loopback is known as internal loopback in the docs
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if (loopback) {
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FDCANx->CCCR |= FDCAN_CCCR_TEST;
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FDCANx->TEST |= FDCAN_TEST_LBCK;
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FDCANx->CCCR |= FDCAN_CCCR_MON;
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}
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// Silent is known as bus monitoring in the docs
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if (silent) {
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FDCANx->CCCR |= FDCAN_CCCR_MON;
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}
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ret = fdcan_exit_init(FDCANx);
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if (!ret) {
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print(CAN_NAME_FROM_CANIF(FDCANx)); print(" set_speed timed out! (2)\n");
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}
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} else {
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print(CAN_NAME_FROM_CANIF(FDCANx)); print(" set_speed timed out! (1)\n");
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}
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return ret;
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}
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void llcan_irq_disable(const FDCAN_GlobalTypeDef *FDCANx) {
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if (FDCANx == FDCAN1) {
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NVIC_DisableIRQ(FDCAN1_IT0_IRQn);
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NVIC_DisableIRQ(FDCAN1_IT1_IRQn);
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} else if (FDCANx == FDCAN2) {
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NVIC_DisableIRQ(FDCAN2_IT0_IRQn);
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NVIC_DisableIRQ(FDCAN2_IT1_IRQn);
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} else if (FDCANx == FDCAN3) {
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NVIC_DisableIRQ(FDCAN3_IT0_IRQn);
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NVIC_DisableIRQ(FDCAN3_IT1_IRQn);
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} else {
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}
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}
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void llcan_irq_enable(const FDCAN_GlobalTypeDef *FDCANx) {
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if (FDCANx == FDCAN1) {
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NVIC_EnableIRQ(FDCAN1_IT0_IRQn);
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NVIC_EnableIRQ(FDCAN1_IT1_IRQn);
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} else if (FDCANx == FDCAN2) {
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NVIC_EnableIRQ(FDCAN2_IT0_IRQn);
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NVIC_EnableIRQ(FDCAN2_IT1_IRQn);
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} else if (FDCANx == FDCAN3) {
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NVIC_EnableIRQ(FDCAN3_IT0_IRQn);
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NVIC_EnableIRQ(FDCAN3_IT1_IRQn);
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} else {
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}
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}
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bool llcan_init(FDCAN_GlobalTypeDef *FDCANx) {
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uint32_t can_number = CAN_NUM_FROM_CANIF(FDCANx);
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bool ret = fdcan_request_init(FDCANx);
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if (ret) {
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// Enable config change
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FDCANx->CCCR |= FDCAN_CCCR_CCE;
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// Enable automatic retransmission
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FDCANx->CCCR &= ~(FDCAN_CCCR_DAR);
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// Enable transmission pause feature
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FDCANx->CCCR |= FDCAN_CCCR_TXP;
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// Disable protocol exception handling
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FDCANx->CCCR |= FDCAN_CCCR_PXHD;
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// FD with BRS
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FDCANx->CCCR |= (FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE);
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// Set TX mode to FIFO
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FDCANx->TXBC &= ~(FDCAN_TXBC_TFQM);
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// Configure TX element data size
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FDCANx->TXESC |= 0x7U << FDCAN_TXESC_TBDS_Pos; // 64 bytes
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//Configure RX FIFO0 element data size
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FDCANx->RXESC |= 0x7U << FDCAN_RXESC_F0DS_Pos;
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// Disable filtering, accept all valid frames received
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FDCANx->XIDFC &= ~(FDCAN_XIDFC_LSE); // No extended filters
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FDCANx->SIDFC &= ~(FDCAN_SIDFC_LSS); // No standard filters
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FDCANx->GFC &= ~(FDCAN_GFC_RRFE); // Accept extended remote frames
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FDCANx->GFC &= ~(FDCAN_GFC_RRFS); // Accept standard remote frames
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FDCANx->GFC &= ~(FDCAN_GFC_ANFE); // Accept extended frames to FIFO 0
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FDCANx->GFC &= ~(FDCAN_GFC_ANFS); // Accept standard frames to FIFO 0
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uint32_t RxFIFO0SA = FDCAN_START_ADDRESS + (can_number * FDCAN_OFFSET);
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uint32_t TxFIFOSA = RxFIFO0SA + (FDCAN_RX_FIFO_0_EL_CNT * FDCAN_RX_FIFO_0_EL_SIZE);
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// RX FIFO 0
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FDCANx->RXF0C |= (FDCAN_RX_FIFO_0_OFFSET + (can_number * FDCAN_OFFSET_W)) << FDCAN_RXF0C_F0SA_Pos;
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FDCANx->RXF0C |= FDCAN_RX_FIFO_0_EL_CNT << FDCAN_RXF0C_F0S_Pos;
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// RX FIFO 0 switch to non-blocking (overwrite) mode
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FDCANx->RXF0C |= FDCAN_RXF0C_F0OM;
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// TX FIFO (mode set earlier)
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FDCANx->TXBC |= (FDCAN_TX_FIFO_OFFSET + (can_number * FDCAN_OFFSET_W)) << FDCAN_TXBC_TBSA_Pos;
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FDCANx->TXBC |= FDCAN_TX_FIFO_EL_CNT << FDCAN_TXBC_TFQS_Pos;
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// Flush allocated RAM
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uint32_t EndAddress = TxFIFOSA + (FDCAN_TX_FIFO_EL_CNT * FDCAN_TX_FIFO_EL_SIZE);
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for (uint32_t RAMcounter = RxFIFO0SA; RAMcounter < EndAddress; RAMcounter += 4U) {
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*(uint32_t *)(RAMcounter) = 0x00000000;
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}
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// Enable both interrupts for each module
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FDCANx->ILE = (FDCAN_ILE_EINT0 | FDCAN_ILE_EINT1);
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FDCANx->IE &= 0x0U; // Reset all interrupts
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// Messages for INT0
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FDCANx->IE |= FDCAN_IE_RF0NE; // Rx FIFO 0 new message
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FDCANx->IE |= FDCAN_IE_PEDE | FDCAN_IE_PEAE | FDCAN_IE_BOE | FDCAN_IE_EPE | FDCAN_IE_RF0LE;
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// Messages for INT1 (Only TFE works??)
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FDCANx->ILS |= FDCAN_ILS_TFEL;
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FDCANx->IE |= FDCAN_IE_TFEE; // Tx FIFO empty
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ret = fdcan_exit_init(FDCANx);
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if(!ret) {
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print(CAN_NAME_FROM_CANIF(FDCANx)); print(" llcan_init timed out (2)!\n");
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}
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llcan_irq_enable(FDCANx);
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} else {
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print(CAN_NAME_FROM_CANIF(FDCANx)); print(" llcan_init timed out (1)!\n");
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}
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return ret;
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}
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void llcan_clear_send(FDCAN_GlobalTypeDef *FDCANx) {
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// from datasheet: "Transmit cancellation is not intended for Tx FIFO operation."
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// so we need to clear pending transmission manually by resetting FDCAN core
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FDCANx->IR |= 0x3FCFFFFFU; // clear all interrupts
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bool ret = llcan_init(FDCANx);
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UNUSED(ret);
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}
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