141 lines
4.1 KiB
C
141 lines
4.1 KiB
C
#include "llbxcan_declarations.h"
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// kbps multiplied by 10
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const uint32_t speeds[SPEEDS_ARRAY_SIZE] = {100U, 200U, 500U, 1000U, 1250U, 2500U, 5000U, 10000U};
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const uint32_t data_speeds[DATA_SPEEDS_ARRAY_SIZE] = {0U}; // No separate data speed, dummy
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bool llcan_set_speed(CAN_TypeDef *CANx, uint32_t speed, bool loopback, bool silent) {
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bool ret = true;
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// initialization mode
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register_set(&(CANx->MCR), CAN_MCR_TTCM | CAN_MCR_INRQ, 0x180FFU);
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uint32_t timeout_counter = 0U;
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while((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK){
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// Delay for about 1ms
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delay(10000);
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timeout_counter++;
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if(timeout_counter >= CAN_INIT_TIMEOUT_MS){
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print(CAN_NAME_FROM_CANIF(CANx)); print(" set_speed timed out (1)!\n");
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ret = false;
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break;
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}
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}
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if(ret){
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// set time quanta from defines
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register_set(&(CANx->BTR), ((CAN_BTR_TS1_0 * (CAN_SEQ1-1U)) |
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(CAN_BTR_TS2_0 * (CAN_SEQ2-1U)) |
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(CAN_BTR_SJW_0 * (CAN_SJW-1U)) |
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(can_speed_to_prescaler(speed) - 1U)), 0xC37F03FFU);
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// silent loopback mode for debugging
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if (loopback) {
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register_set_bits(&(CANx->BTR), CAN_BTR_SILM | CAN_BTR_LBKM);
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}
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if (silent) {
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register_set_bits(&(CANx->BTR), CAN_BTR_SILM);
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}
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// reset
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register_set(&(CANx->MCR), CAN_MCR_TTCM | CAN_MCR_ABOM, 0x180FFU);
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timeout_counter = 0U;
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while(((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)) {
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// Delay for about 1ms
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delay(10000);
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timeout_counter++;
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if(timeout_counter >= CAN_INIT_TIMEOUT_MS){
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print(CAN_NAME_FROM_CANIF(CANx)); print(" set_speed timed out (2)!\n");
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ret = false;
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break;
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}
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}
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}
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return ret;
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}
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void llcan_irq_disable(const CAN_TypeDef *CANx) {
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if (CANx == CAN1) {
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NVIC_DisableIRQ(CAN1_TX_IRQn);
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NVIC_DisableIRQ(CAN1_RX0_IRQn);
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NVIC_DisableIRQ(CAN1_SCE_IRQn);
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} else if (CANx == CAN2) {
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NVIC_DisableIRQ(CAN2_TX_IRQn);
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NVIC_DisableIRQ(CAN2_RX0_IRQn);
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NVIC_DisableIRQ(CAN2_SCE_IRQn);
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} else if (CANx == CAN3) {
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NVIC_DisableIRQ(CAN3_TX_IRQn);
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NVIC_DisableIRQ(CAN3_RX0_IRQn);
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NVIC_DisableIRQ(CAN3_SCE_IRQn);
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} else {
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}
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}
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void llcan_irq_enable(const CAN_TypeDef *CANx) {
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if (CANx == CAN1) {
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NVIC_EnableIRQ(CAN1_TX_IRQn);
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NVIC_EnableIRQ(CAN1_RX0_IRQn);
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NVIC_EnableIRQ(CAN1_SCE_IRQn);
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} else if (CANx == CAN2) {
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NVIC_EnableIRQ(CAN2_TX_IRQn);
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NVIC_EnableIRQ(CAN2_RX0_IRQn);
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NVIC_EnableIRQ(CAN2_SCE_IRQn);
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} else if (CANx == CAN3) {
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NVIC_EnableIRQ(CAN3_TX_IRQn);
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NVIC_EnableIRQ(CAN3_RX0_IRQn);
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NVIC_EnableIRQ(CAN3_SCE_IRQn);
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} else {
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}
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}
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bool llcan_init(CAN_TypeDef *CANx) {
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bool ret = true;
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// Enter init mode
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register_set_bits(&(CANx->FMR), CAN_FMR_FINIT);
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// Wait for INAK bit to be set
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uint32_t timeout_counter = 0U;
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while(((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)) {
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// Delay for about 1ms
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delay(10000);
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timeout_counter++;
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if(timeout_counter >= CAN_INIT_TIMEOUT_MS){
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print(CAN_NAME_FROM_CANIF(CANx)); print(" initialization timed out!\n");
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ret = false;
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break;
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}
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}
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if(ret){
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// no mask
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// For some weird reason some of these registers do not want to set properly on CAN2 and CAN3. Probably something to do with the single/dual mode and their different filters.
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CANx->sFilterRegister[0].FR1 = 0U;
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CANx->sFilterRegister[0].FR2 = 0U;
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CANx->sFilterRegister[14].FR1 = 0U;
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CANx->sFilterRegister[14].FR2 = 0U;
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CANx->FA1R |= 1U | (1UL << 14);
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// Exit init mode, do not wait
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register_clear_bits(&(CANx->FMR), CAN_FMR_FINIT);
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// enable certain CAN interrupts
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register_set_bits(&(CANx->IER), CAN_IER_TMEIE | CAN_IER_FMPIE0 | CAN_IER_ERRIE | CAN_IER_LECIE | CAN_IER_BOFIE | CAN_IER_EPVIE | CAN_IER_EWGIE | CAN_IER_FOVIE0 | CAN_IER_FFIE0);
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// clear overrun flag on init
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CANx->RF0R &= ~(CAN_RF0R_FOVR0);
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llcan_irq_enable(CANx);
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}
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return ret;
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}
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void llcan_clear_send(CAN_TypeDef *CANx) {
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CANx->TSR |= CAN_TSR_ABRQ0; // Abort message transmission on error interrupt
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CANx->MSR |= CAN_MSR_ERRI; // Clear error interrupt
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}
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