1639 lines
76 KiB
Python
1639 lines
76 KiB
Python
# -*- coding: utf-8 -*-
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#
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# TARGET arch is: []
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# WORD_SIZE is: 8
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# POINTER_SIZE is: 8
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# LONGDOUBLE_SIZE is: 16
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#
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import ctypes
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_mp_11_0_2_OFFSET_HEADER = True # macro
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mmMP0_SMN_C2PMSG_32 = 0x0060 # macro
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mmMP0_SMN_C2PMSG_32_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_33 = 0x0061 # macro
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mmMP0_SMN_C2PMSG_33_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_34 = 0x0062 # macro
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mmMP0_SMN_C2PMSG_34_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_35 = 0x0063 # macro
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mmMP0_SMN_C2PMSG_35_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_36 = 0x0064 # macro
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mmMP0_SMN_C2PMSG_36_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_37 = 0x0065 # macro
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mmMP0_SMN_C2PMSG_37_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_38 = 0x0066 # macro
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mmMP0_SMN_C2PMSG_38_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_39 = 0x0067 # macro
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mmMP0_SMN_C2PMSG_39_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_40 = 0x0068 # macro
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mmMP0_SMN_C2PMSG_40_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_41 = 0x0069 # macro
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mmMP0_SMN_C2PMSG_41_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_42 = 0x006a # macro
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mmMP0_SMN_C2PMSG_42_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_43 = 0x006b # macro
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mmMP0_SMN_C2PMSG_43_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_44 = 0x006c # macro
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mmMP0_SMN_C2PMSG_44_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_45 = 0x006d # macro
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mmMP0_SMN_C2PMSG_45_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_46 = 0x006e # macro
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mmMP0_SMN_C2PMSG_46_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_47 = 0x006f # macro
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mmMP0_SMN_C2PMSG_47_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_48 = 0x0070 # macro
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mmMP0_SMN_C2PMSG_48_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_49 = 0x0071 # macro
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mmMP0_SMN_C2PMSG_49_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_50 = 0x0072 # macro
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mmMP0_SMN_C2PMSG_50_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_51 = 0x0073 # macro
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mmMP0_SMN_C2PMSG_51_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_52 = 0x0074 # macro
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mmMP0_SMN_C2PMSG_52_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_53 = 0x0075 # macro
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mmMP0_SMN_C2PMSG_53_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_54 = 0x0076 # macro
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mmMP0_SMN_C2PMSG_54_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_55 = 0x0077 # macro
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mmMP0_SMN_C2PMSG_55_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_56 = 0x0078 # macro
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mmMP0_SMN_C2PMSG_56_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_57 = 0x0079 # macro
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mmMP0_SMN_C2PMSG_57_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_58 = 0x007a # macro
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mmMP0_SMN_C2PMSG_58_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_59 = 0x007b # macro
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mmMP0_SMN_C2PMSG_59_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_60 = 0x007c # macro
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mmMP0_SMN_C2PMSG_60_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_61 = 0x007d # macro
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mmMP0_SMN_C2PMSG_61_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_62 = 0x007e # macro
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mmMP0_SMN_C2PMSG_62_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_63 = 0x007f # macro
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mmMP0_SMN_C2PMSG_63_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_64 = 0x0080 # macro
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mmMP0_SMN_C2PMSG_64_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_65 = 0x0081 # macro
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mmMP0_SMN_C2PMSG_65_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_66 = 0x0082 # macro
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mmMP0_SMN_C2PMSG_66_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_67 = 0x0083 # macro
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mmMP0_SMN_C2PMSG_67_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_68 = 0x0084 # macro
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mmMP0_SMN_C2PMSG_68_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_69 = 0x0085 # macro
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mmMP0_SMN_C2PMSG_69_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_70 = 0x0086 # macro
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mmMP0_SMN_C2PMSG_70_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_71 = 0x0087 # macro
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mmMP0_SMN_C2PMSG_71_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_72 = 0x0088 # macro
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mmMP0_SMN_C2PMSG_72_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_73 = 0x0089 # macro
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mmMP0_SMN_C2PMSG_73_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_74 = 0x008a # macro
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mmMP0_SMN_C2PMSG_74_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_75 = 0x008b # macro
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mmMP0_SMN_C2PMSG_75_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_76 = 0x008c # macro
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mmMP0_SMN_C2PMSG_76_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_77 = 0x008d # macro
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mmMP0_SMN_C2PMSG_77_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_78 = 0x008e # macro
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mmMP0_SMN_C2PMSG_78_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_79 = 0x008f # macro
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mmMP0_SMN_C2PMSG_79_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_80 = 0x0090 # macro
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mmMP0_SMN_C2PMSG_80_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_81 = 0x0091 # macro
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mmMP0_SMN_C2PMSG_81_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_82 = 0x0092 # macro
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mmMP0_SMN_C2PMSG_82_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_83 = 0x0093 # macro
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mmMP0_SMN_C2PMSG_83_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_84 = 0x0094 # macro
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mmMP0_SMN_C2PMSG_84_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_85 = 0x0095 # macro
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mmMP0_SMN_C2PMSG_85_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_86 = 0x0096 # macro
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mmMP0_SMN_C2PMSG_86_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_87 = 0x0097 # macro
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mmMP0_SMN_C2PMSG_87_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_88 = 0x0098 # macro
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mmMP0_SMN_C2PMSG_88_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_89 = 0x0099 # macro
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mmMP0_SMN_C2PMSG_89_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_90 = 0x009a # macro
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mmMP0_SMN_C2PMSG_90_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_91 = 0x009b # macro
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mmMP0_SMN_C2PMSG_91_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_92 = 0x009c # macro
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mmMP0_SMN_C2PMSG_92_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_93 = 0x009d # macro
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mmMP0_SMN_C2PMSG_93_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_94 = 0x009e # macro
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mmMP0_SMN_C2PMSG_94_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_95 = 0x009f # macro
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mmMP0_SMN_C2PMSG_95_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_96 = 0x00a0 # macro
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mmMP0_SMN_C2PMSG_96_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_97 = 0x00a1 # macro
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mmMP0_SMN_C2PMSG_97_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_98 = 0x00a2 # macro
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mmMP0_SMN_C2PMSG_98_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_99 = 0x00a3 # macro
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mmMP0_SMN_C2PMSG_99_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_100 = 0x00a4 # macro
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mmMP0_SMN_C2PMSG_100_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_101 = 0x00a5 # macro
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mmMP0_SMN_C2PMSG_101_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_102 = 0x00a6 # macro
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mmMP0_SMN_C2PMSG_102_BASE_IDX = 0 # macro
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mmMP0_SMN_C2PMSG_103 = 0x00a7 # macro
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mmMP0_SMN_C2PMSG_103_BASE_IDX = 0 # macro
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mmMP0_SMN_ACTIVE_FCN_ID = 0x00c0 # macro
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mmMP0_SMN_ACTIVE_FCN_ID_BASE_IDX = 0 # macro
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mmMP0_SMN_IH_CREDIT = 0x00c1 # macro
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mmMP0_SMN_IH_CREDIT_BASE_IDX = 0 # macro
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mmMP0_SMN_IH_SW_INT = 0x00c2 # macro
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mmMP0_SMN_IH_SW_INT_BASE_IDX = 0 # macro
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mmMP0_SMN_IH_SW_INT_CTRL = 0x00c3 # macro
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mmMP0_SMN_IH_SW_INT_CTRL_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_32 = 0x0260 # macro
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mmMP1_SMN_C2PMSG_32_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_33 = 0x0261 # macro
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mmMP1_SMN_C2PMSG_33_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_34 = 0x0262 # macro
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mmMP1_SMN_C2PMSG_34_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_35 = 0x0263 # macro
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mmMP1_SMN_C2PMSG_35_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_36 = 0x0264 # macro
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mmMP1_SMN_C2PMSG_36_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_37 = 0x0265 # macro
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mmMP1_SMN_C2PMSG_37_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_38 = 0x0266 # macro
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mmMP1_SMN_C2PMSG_38_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_39 = 0x0267 # macro
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mmMP1_SMN_C2PMSG_39_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_40 = 0x0268 # macro
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mmMP1_SMN_C2PMSG_40_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_41 = 0x0269 # macro
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mmMP1_SMN_C2PMSG_41_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_42 = 0x026a # macro
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mmMP1_SMN_C2PMSG_42_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_43 = 0x026b # macro
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mmMP1_SMN_C2PMSG_43_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_44 = 0x026c # macro
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mmMP1_SMN_C2PMSG_44_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_45 = 0x026d # macro
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mmMP1_SMN_C2PMSG_45_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_46 = 0x026e # macro
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mmMP1_SMN_C2PMSG_46_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_47 = 0x026f # macro
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mmMP1_SMN_C2PMSG_47_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_48 = 0x0270 # macro
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mmMP1_SMN_C2PMSG_48_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_49 = 0x0271 # macro
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mmMP1_SMN_C2PMSG_49_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_50 = 0x0272 # macro
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mmMP1_SMN_C2PMSG_50_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_51 = 0x0273 # macro
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mmMP1_SMN_C2PMSG_51_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_52 = 0x0274 # macro
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mmMP1_SMN_C2PMSG_52_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_53 = 0x0275 # macro
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mmMP1_SMN_C2PMSG_53_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_54 = 0x0276 # macro
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mmMP1_SMN_C2PMSG_54_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_55 = 0x0277 # macro
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mmMP1_SMN_C2PMSG_55_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_56 = 0x0278 # macro
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mmMP1_SMN_C2PMSG_56_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_57 = 0x0279 # macro
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mmMP1_SMN_C2PMSG_57_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_58 = 0x027a # macro
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mmMP1_SMN_C2PMSG_58_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_59 = 0x027b # macro
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mmMP1_SMN_C2PMSG_59_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_60 = 0x027c # macro
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mmMP1_SMN_C2PMSG_60_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_61 = 0x027d # macro
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mmMP1_SMN_C2PMSG_61_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_62 = 0x027e # macro
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mmMP1_SMN_C2PMSG_62_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_63 = 0x027f # macro
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mmMP1_SMN_C2PMSG_63_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_64 = 0x0280 # macro
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mmMP1_SMN_C2PMSG_64_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_65 = 0x0281 # macro
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mmMP1_SMN_C2PMSG_65_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_66 = 0x0282 # macro
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mmMP1_SMN_C2PMSG_66_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_67 = 0x0283 # macro
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mmMP1_SMN_C2PMSG_67_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_68 = 0x0284 # macro
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mmMP1_SMN_C2PMSG_68_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_69 = 0x0285 # macro
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mmMP1_SMN_C2PMSG_69_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_70 = 0x0286 # macro
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mmMP1_SMN_C2PMSG_70_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_71 = 0x0287 # macro
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mmMP1_SMN_C2PMSG_71_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_72 = 0x0288 # macro
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mmMP1_SMN_C2PMSG_72_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_73 = 0x0289 # macro
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mmMP1_SMN_C2PMSG_73_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_74 = 0x028a # macro
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mmMP1_SMN_C2PMSG_74_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_75 = 0x028b # macro
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mmMP1_SMN_C2PMSG_75_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_76 = 0x028c # macro
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mmMP1_SMN_C2PMSG_76_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_77 = 0x028d # macro
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mmMP1_SMN_C2PMSG_77_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_78 = 0x028e # macro
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mmMP1_SMN_C2PMSG_78_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_79 = 0x028f # macro
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mmMP1_SMN_C2PMSG_79_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_80 = 0x0290 # macro
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mmMP1_SMN_C2PMSG_80_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_81 = 0x0291 # macro
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mmMP1_SMN_C2PMSG_81_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_82 = 0x0292 # macro
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mmMP1_SMN_C2PMSG_82_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_83 = 0x0293 # macro
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mmMP1_SMN_C2PMSG_83_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_84 = 0x0294 # macro
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mmMP1_SMN_C2PMSG_84_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_85 = 0x0295 # macro
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mmMP1_SMN_C2PMSG_85_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_86 = 0x0296 # macro
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mmMP1_SMN_C2PMSG_86_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_87 = 0x0297 # macro
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mmMP1_SMN_C2PMSG_87_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_88 = 0x0298 # macro
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mmMP1_SMN_C2PMSG_88_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_89 = 0x0299 # macro
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mmMP1_SMN_C2PMSG_89_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_90 = 0x029a # macro
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mmMP1_SMN_C2PMSG_90_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_91 = 0x029b # macro
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mmMP1_SMN_C2PMSG_91_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_92 = 0x029c # macro
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mmMP1_SMN_C2PMSG_92_BASE_IDX = 0 # macro
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mmMP1_SMN_C2PMSG_93 = 0x029d # macro
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mmMP1_SMN_C2PMSG_93_BASE_IDX = 0 # macro
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|
mmMP1_SMN_C2PMSG_94 = 0x029e # macro
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mmMP1_SMN_C2PMSG_94_BASE_IDX = 0 # macro
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|
mmMP1_SMN_C2PMSG_95 = 0x029f # macro
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|
mmMP1_SMN_C2PMSG_95_BASE_IDX = 0 # macro
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|
mmMP1_SMN_C2PMSG_96 = 0x02a0 # macro
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|
mmMP1_SMN_C2PMSG_96_BASE_IDX = 0 # macro
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|
mmMP1_SMN_C2PMSG_97 = 0x02a1 # macro
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|
mmMP1_SMN_C2PMSG_97_BASE_IDX = 0 # macro
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|
mmMP1_SMN_C2PMSG_98 = 0x02a2 # macro
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|
mmMP1_SMN_C2PMSG_98_BASE_IDX = 0 # macro
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|
mmMP1_SMN_C2PMSG_99 = 0x02a3 # macro
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mmMP1_SMN_C2PMSG_99_BASE_IDX = 0 # macro
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|
mmMP1_SMN_C2PMSG_100 = 0x02a4 # macro
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|
mmMP1_SMN_C2PMSG_100_BASE_IDX = 0 # macro
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|
mmMP1_SMN_C2PMSG_101 = 0x02a5 # macro
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|
mmMP1_SMN_C2PMSG_101_BASE_IDX = 0 # macro
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|
mmMP1_SMN_C2PMSG_102 = 0x02a6 # macro
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|
mmMP1_SMN_C2PMSG_102_BASE_IDX = 0 # macro
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|
mmMP1_SMN_C2PMSG_103 = 0x02a7 # macro
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|
mmMP1_SMN_C2PMSG_103_BASE_IDX = 0 # macro
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|
mmMP1_SMN_ACTIVE_FCN_ID = 0x02c0 # macro
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|
mmMP1_SMN_ACTIVE_FCN_ID_BASE_IDX = 0 # macro
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|
mmMP1_SMN_IH_CREDIT = 0x02c1 # macro
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|
mmMP1_SMN_IH_CREDIT_BASE_IDX = 0 # macro
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|
mmMP1_SMN_IH_SW_INT = 0x02c2 # macro
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|
mmMP1_SMN_IH_SW_INT_BASE_IDX = 0 # macro
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|
mmMP1_SMN_IH_SW_INT_CTRL = 0x02c3 # macro
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|
mmMP1_SMN_IH_SW_INT_CTRL_BASE_IDX = 0 # macro
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|
mmMP1_SMN_FPS_CNT = 0x02c4 # macro
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mmMP1_SMN_FPS_CNT_BASE_IDX = 0 # macro
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mmMP1_SMN_PUB_CTRL = 0x02c5 # macro
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|
mmMP1_SMN_PUB_CTRL_BASE_IDX = 0 # macro
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mmMP1_SMN_EXT_SCRATCH0 = 0x03c0 # macro
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|
mmMP1_SMN_EXT_SCRATCH0_BASE_IDX = 0 # macro
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|
mmMP1_SMN_EXT_SCRATCH1 = 0x03c1 # macro
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|
mmMP1_SMN_EXT_SCRATCH1_BASE_IDX = 0 # macro
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|
mmMP1_SMN_EXT_SCRATCH2 = 0x03c2 # macro
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|
mmMP1_SMN_EXT_SCRATCH2_BASE_IDX = 0 # macro
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|
mmMP1_SMN_EXT_SCRATCH3 = 0x03c3 # macro
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|
mmMP1_SMN_EXT_SCRATCH3_BASE_IDX = 0 # macro
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|
mmMP1_SMN_EXT_SCRATCH4 = 0x03c4 # macro
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|
mmMP1_SMN_EXT_SCRATCH4_BASE_IDX = 0 # macro
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|
mmMP1_SMN_EXT_SCRATCH5 = 0x03c5 # macro
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|
mmMP1_SMN_EXT_SCRATCH5_BASE_IDX = 0 # macro
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|
mmMP1_SMN_EXT_SCRATCH6 = 0x03c6 # macro
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|
mmMP1_SMN_EXT_SCRATCH6_BASE_IDX = 0 # macro
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|
mmMP1_SMN_EXT_SCRATCH7 = 0x03c7 # macro
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|
mmMP1_SMN_EXT_SCRATCH7_BASE_IDX = 0 # macro
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|
smnMP1_PMI_3_START = 0x3030204 # macro
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|
smnMP1_PMI_3_FIFO = 0x3030208 # macro
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|
smnMP1_PMI_3 = 0x3030600 # macro
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|
_mp_11_0_2_SH_MASK_HEADER = True # macro
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|
MP0_SMN_C2PMSG_32__CONTENT__SHIFT = 0x0 # macro
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|
MP0_SMN_C2PMSG_32__CONTENT_MASK = 0xFFFFFFFF # macro
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|
MP0_SMN_C2PMSG_33__CONTENT__SHIFT = 0x0 # macro
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|
MP0_SMN_C2PMSG_33__CONTENT_MASK = 0xFFFFFFFF # macro
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|
MP0_SMN_C2PMSG_34__CONTENT__SHIFT = 0x0 # macro
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|
MP0_SMN_C2PMSG_34__CONTENT_MASK = 0xFFFFFFFF # macro
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|
MP0_SMN_C2PMSG_35__CONTENT__SHIFT = 0x0 # macro
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|
MP0_SMN_C2PMSG_35__CONTENT_MASK = 0xFFFFFFFF # macro
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|
MP0_SMN_C2PMSG_36__CONTENT__SHIFT = 0x0 # macro
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|
MP0_SMN_C2PMSG_36__CONTENT_MASK = 0xFFFFFFFF # macro
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|
MP0_SMN_C2PMSG_37__CONTENT__SHIFT = 0x0 # macro
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|
MP0_SMN_C2PMSG_37__CONTENT_MASK = 0xFFFFFFFF # macro
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|
MP0_SMN_C2PMSG_38__CONTENT__SHIFT = 0x0 # macro
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|
MP0_SMN_C2PMSG_38__CONTENT_MASK = 0xFFFFFFFF # macro
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|
MP0_SMN_C2PMSG_39__CONTENT__SHIFT = 0x0 # macro
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|
MP0_SMN_C2PMSG_39__CONTENT_MASK = 0xFFFFFFFF # macro
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|
MP0_SMN_C2PMSG_40__CONTENT__SHIFT = 0x0 # macro
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|
MP0_SMN_C2PMSG_40__CONTENT_MASK = 0xFFFFFFFF # macro
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|
MP0_SMN_C2PMSG_41__CONTENT__SHIFT = 0x0 # macro
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|
MP0_SMN_C2PMSG_41__CONTENT_MASK = 0xFFFFFFFF # macro
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|
MP0_SMN_C2PMSG_42__CONTENT__SHIFT = 0x0 # macro
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|
MP0_SMN_C2PMSG_42__CONTENT_MASK = 0xFFFFFFFF # macro
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|
MP0_SMN_C2PMSG_43__CONTENT__SHIFT = 0x0 # macro
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|
MP0_SMN_C2PMSG_43__CONTENT_MASK = 0xFFFFFFFF # macro
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|
MP0_SMN_C2PMSG_44__CONTENT__SHIFT = 0x0 # macro
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|
MP0_SMN_C2PMSG_44__CONTENT_MASK = 0xFFFFFFFF # macro
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|
MP0_SMN_C2PMSG_45__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_45__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_46__CONTENT__SHIFT = 0x0 # macro
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|
MP0_SMN_C2PMSG_46__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_47__CONTENT__SHIFT = 0x0 # macro
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|
MP0_SMN_C2PMSG_47__CONTENT_MASK = 0xFFFFFFFF # macro
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|
MP0_SMN_C2PMSG_48__CONTENT__SHIFT = 0x0 # macro
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|
MP0_SMN_C2PMSG_48__CONTENT_MASK = 0xFFFFFFFF # macro
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|
MP0_SMN_C2PMSG_49__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_49__CONTENT_MASK = 0xFFFFFFFF # macro
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|
MP0_SMN_C2PMSG_50__CONTENT__SHIFT = 0x0 # macro
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|
MP0_SMN_C2PMSG_50__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_51__CONTENT__SHIFT = 0x0 # macro
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|
MP0_SMN_C2PMSG_51__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_52__CONTENT__SHIFT = 0x0 # macro
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|
MP0_SMN_C2PMSG_52__CONTENT_MASK = 0xFFFFFFFF # macro
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|
MP0_SMN_C2PMSG_53__CONTENT__SHIFT = 0x0 # macro
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|
MP0_SMN_C2PMSG_53__CONTENT_MASK = 0xFFFFFFFF # macro
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|
MP0_SMN_C2PMSG_54__CONTENT__SHIFT = 0x0 # macro
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|
MP0_SMN_C2PMSG_54__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_55__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_55__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_56__CONTENT__SHIFT = 0x0 # macro
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|
MP0_SMN_C2PMSG_56__CONTENT_MASK = 0xFFFFFFFF # macro
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|
MP0_SMN_C2PMSG_57__CONTENT__SHIFT = 0x0 # macro
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|
MP0_SMN_C2PMSG_57__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_58__CONTENT__SHIFT = 0x0 # macro
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|
MP0_SMN_C2PMSG_58__CONTENT_MASK = 0xFFFFFFFF # macro
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|
MP0_SMN_C2PMSG_59__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_59__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_60__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_60__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_61__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_61__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_62__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_62__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_63__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_63__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_64__CONTENT__SHIFT = 0x0 # macro
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|
MP0_SMN_C2PMSG_64__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_65__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_65__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_66__CONTENT__SHIFT = 0x0 # macro
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|
MP0_SMN_C2PMSG_66__CONTENT_MASK = 0xFFFFFFFF # macro
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|
MP0_SMN_C2PMSG_67__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_67__CONTENT_MASK = 0xFFFFFFFF # macro
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|
MP0_SMN_C2PMSG_68__CONTENT__SHIFT = 0x0 # macro
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|
MP0_SMN_C2PMSG_68__CONTENT_MASK = 0xFFFFFFFF # macro
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|
MP0_SMN_C2PMSG_69__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_69__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_70__CONTENT__SHIFT = 0x0 # macro
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|
MP0_SMN_C2PMSG_70__CONTENT_MASK = 0xFFFFFFFF # macro
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|
MP0_SMN_C2PMSG_71__CONTENT__SHIFT = 0x0 # macro
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|
MP0_SMN_C2PMSG_71__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_72__CONTENT__SHIFT = 0x0 # macro
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|
MP0_SMN_C2PMSG_72__CONTENT_MASK = 0xFFFFFFFF # macro
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|
MP0_SMN_C2PMSG_73__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_73__CONTENT_MASK = 0xFFFFFFFF # macro
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|
MP0_SMN_C2PMSG_74__CONTENT__SHIFT = 0x0 # macro
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|
MP0_SMN_C2PMSG_74__CONTENT_MASK = 0xFFFFFFFF # macro
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|
MP0_SMN_C2PMSG_75__CONTENT__SHIFT = 0x0 # macro
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|
MP0_SMN_C2PMSG_75__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_76__CONTENT__SHIFT = 0x0 # macro
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|
MP0_SMN_C2PMSG_76__CONTENT_MASK = 0xFFFFFFFF # macro
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|
MP0_SMN_C2PMSG_77__CONTENT__SHIFT = 0x0 # macro
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|
MP0_SMN_C2PMSG_77__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_78__CONTENT__SHIFT = 0x0 # macro
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|
MP0_SMN_C2PMSG_78__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_79__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_79__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_80__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_80__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_81__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_81__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_82__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_82__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_83__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_83__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_84__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_84__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_85__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_85__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_86__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_86__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_87__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_87__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_88__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_88__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_89__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_89__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_90__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_90__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_91__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_91__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_92__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_92__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_93__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_93__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_94__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_94__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_95__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_95__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_96__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_96__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_97__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_97__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_98__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_98__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_99__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_99__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_100__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_100__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_101__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_101__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_102__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_102__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_C2PMSG_103__CONTENT__SHIFT = 0x0 # macro
|
|
MP0_SMN_C2PMSG_103__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP0_SMN_ACTIVE_FCN_ID__VFID__SHIFT = 0x0 # macro
|
|
MP0_SMN_ACTIVE_FCN_ID__VF__SHIFT = 0x1f # macro
|
|
MP0_SMN_ACTIVE_FCN_ID__VFID_MASK = 0x0000001F # macro
|
|
MP0_SMN_ACTIVE_FCN_ID__VF_MASK = 0x80000000 # macro
|
|
MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT = 0x0 # macro
|
|
MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT = 0x10 # macro
|
|
MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK = 0x00000003 # macro
|
|
MP0_SMN_IH_CREDIT__CLIENT_ID_MASK = 0x00FF0000 # macro
|
|
MP0_SMN_IH_SW_INT__ID__SHIFT = 0x0 # macro
|
|
MP0_SMN_IH_SW_INT__VALID__SHIFT = 0x8 # macro
|
|
MP0_SMN_IH_SW_INT__ID_MASK = 0x000000FF # macro
|
|
MP0_SMN_IH_SW_INT__VALID_MASK = 0x00000100 # macro
|
|
MP0_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT = 0x0 # macro
|
|
MP0_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT = 0x8 # macro
|
|
MP0_SMN_IH_SW_INT_CTRL__INT_MASK_MASK = 0x00000001 # macro
|
|
MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK = 0x00000100 # macro
|
|
MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT = 0x0 # macro
|
|
MP1_FIRMWARE_FLAGS__RESERVED__SHIFT = 0x1 # macro
|
|
MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK = 0x00000001 # macro
|
|
MP1_FIRMWARE_FLAGS__RESERVED_MASK = 0xFFFFFFFE # macro
|
|
MP1_PUB_SCRATCH0__DATA__SHIFT = 0x0 # macro
|
|
MP1_PUB_SCRATCH0__DATA_MASK = 0xFFFFFFFF # macro
|
|
MP1_PUB_SCRATCH1__DATA__SHIFT = 0x0 # macro
|
|
MP1_PUB_SCRATCH1__DATA_MASK = 0xFFFFFFFF # macro
|
|
MP1_PUB_SCRATCH2__DATA__SHIFT = 0x0 # macro
|
|
MP1_PUB_SCRATCH2__DATA_MASK = 0xFFFFFFFF # macro
|
|
MP1_PUB_SCRATCH3__DATA__SHIFT = 0x0 # macro
|
|
MP1_PUB_SCRATCH3__DATA_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_0__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_0__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_1__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_1__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_2__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_2__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_3__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_3__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_4__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_4__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_5__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_5__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_6__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_6__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_7__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_7__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_8__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_8__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_9__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_9__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_10__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_10__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_11__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_11__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_12__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_12__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_13__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_13__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_14__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_14__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_15__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_15__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_16__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_16__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_17__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_17__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_18__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_18__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_19__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_19__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_20__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_20__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_21__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_21__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_22__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_22__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_23__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_23__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_24__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_24__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_25__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_25__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_26__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_26__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_27__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_27__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_28__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_28__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_29__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_29__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_30__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_30__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_31__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_31__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_P2CMSG_0__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_P2CMSG_0__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_P2CMSG_1__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_P2CMSG_1__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_P2CMSG_2__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_P2CMSG_2__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_P2CMSG_3__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_P2CMSG_3__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_P2CMSG_INTEN__INTEN__SHIFT = 0x0 # macro
|
|
MP1_P2CMSG_INTEN__INTEN_MASK = 0x0000000F # macro
|
|
MP1_P2CMSG_INTSTS__INTSTS0__SHIFT = 0x0 # macro
|
|
MP1_P2CMSG_INTSTS__INTSTS1__SHIFT = 0x1 # macro
|
|
MP1_P2CMSG_INTSTS__INTSTS2__SHIFT = 0x2 # macro
|
|
MP1_P2CMSG_INTSTS__INTSTS3__SHIFT = 0x3 # macro
|
|
MP1_P2CMSG_INTSTS__INTSTS0_MASK = 0x00000001 # macro
|
|
MP1_P2CMSG_INTSTS__INTSTS1_MASK = 0x00000002 # macro
|
|
MP1_P2CMSG_INTSTS__INTSTS2_MASK = 0x00000004 # macro
|
|
MP1_P2CMSG_INTSTS__INTSTS3_MASK = 0x00000008 # macro
|
|
MP1_P2SMSG_0__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_P2SMSG_0__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_P2SMSG_1__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_P2SMSG_1__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_P2SMSG_2__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_P2SMSG_2__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_P2SMSG_3__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_P2SMSG_3__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_P2SMSG_INTSTS__INTSTS0__SHIFT = 0x0 # macro
|
|
MP1_P2SMSG_INTSTS__INTSTS1__SHIFT = 0x1 # macro
|
|
MP1_P2SMSG_INTSTS__INTSTS2__SHIFT = 0x2 # macro
|
|
MP1_P2SMSG_INTSTS__INTSTS3__SHIFT = 0x3 # macro
|
|
MP1_P2SMSG_INTSTS__INTSTS0_MASK = 0x00000001 # macro
|
|
MP1_P2SMSG_INTSTS__INTSTS1_MASK = 0x00000002 # macro
|
|
MP1_P2SMSG_INTSTS__INTSTS2_MASK = 0x00000004 # macro
|
|
MP1_P2SMSG_INTSTS__INTSTS3_MASK = 0x00000008 # macro
|
|
MP1_S2PMSG_0__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_S2PMSG_0__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_32__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_32__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_33__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_33__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_34__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_34__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_35__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_35__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_36__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_36__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_37__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_37__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_38__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_38__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_39__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_39__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_40__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_40__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_41__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_41__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_42__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_42__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_43__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_43__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_44__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_44__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_45__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_45__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_46__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_46__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_47__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_47__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_48__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_48__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_49__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_49__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_50__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_50__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_51__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_51__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_52__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_52__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_53__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_53__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_54__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_54__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_55__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_55__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_56__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_56__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_57__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_57__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_58__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_58__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_59__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_59__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_60__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_60__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_61__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_61__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_62__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_62__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_63__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_63__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_64__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_64__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_65__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_65__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_66__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_66__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_67__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_67__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_68__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_68__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_69__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_69__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_70__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_70__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_71__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_71__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_72__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_72__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_73__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_73__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_74__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_74__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_75__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_75__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_76__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_76__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_77__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_77__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_78__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_78__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_79__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_79__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_80__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_80__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_81__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_81__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_82__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_82__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_83__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_83__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_84__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_84__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_85__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_85__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_86__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_86__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_87__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_87__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_88__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_88__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_89__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_89__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_90__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_90__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_91__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_91__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_92__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_92__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_93__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_93__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_94__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_94__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_95__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_95__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_96__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_96__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_97__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_97__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_98__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_98__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_99__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_99__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_100__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_100__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_101__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_101__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_102__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_102__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_C2PMSG_103__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_C2PMSG_103__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_ACTIVE_FCN_ID__VFID__SHIFT = 0x0 # macro
|
|
MP1_ACTIVE_FCN_ID__VF__SHIFT = 0x1f # macro
|
|
MP1_ACTIVE_FCN_ID__VFID_MASK = 0x0000001F # macro
|
|
MP1_ACTIVE_FCN_ID__VF_MASK = 0x80000000 # macro
|
|
MP1_IH_CREDIT__CREDIT_VALUE__SHIFT = 0x0 # macro
|
|
MP1_IH_CREDIT__CLIENT_ID__SHIFT = 0x10 # macro
|
|
MP1_IH_CREDIT__CREDIT_VALUE_MASK = 0x00000003 # macro
|
|
MP1_IH_CREDIT__CLIENT_ID_MASK = 0x00FF0000 # macro
|
|
MP1_IH_SW_INT__ID__SHIFT = 0x0 # macro
|
|
MP1_IH_SW_INT__VALID__SHIFT = 0x8 # macro
|
|
MP1_IH_SW_INT__ID_MASK = 0x000000FF # macro
|
|
MP1_IH_SW_INT__VALID_MASK = 0x00000100 # macro
|
|
MP1_IH_SW_INT_CTRL__INT_MASK__SHIFT = 0x0 # macro
|
|
MP1_IH_SW_INT_CTRL__INT_ACK__SHIFT = 0x8 # macro
|
|
MP1_IH_SW_INT_CTRL__INT_MASK_MASK = 0x00000001 # macro
|
|
MP1_IH_SW_INT_CTRL__INT_ACK_MASK = 0x00000100 # macro
|
|
MP1_FPS_CNT__COUNT__SHIFT = 0x0 # macro
|
|
MP1_FPS_CNT__COUNT_MASK = 0xFFFFFFFF # macro
|
|
MP1_PUB_CTRL__RESET__SHIFT = 0x0 # macro
|
|
MP1_PUB_CTRL__RESET_MASK = 0x00000001 # macro
|
|
MP1_EXT_SCRATCH0__DATA__SHIFT = 0x0 # macro
|
|
MP1_EXT_SCRATCH0__DATA_MASK = 0xFFFFFFFF # macro
|
|
MP1_EXT_SCRATCH1__DATA__SHIFT = 0x0 # macro
|
|
MP1_EXT_SCRATCH1__DATA_MASK = 0xFFFFFFFF # macro
|
|
MP1_EXT_SCRATCH2__DATA__SHIFT = 0x0 # macro
|
|
MP1_EXT_SCRATCH2__DATA_MASK = 0xFFFFFFFF # macro
|
|
MP1_EXT_SCRATCH3__DATA__SHIFT = 0x0 # macro
|
|
MP1_EXT_SCRATCH3__DATA_MASK = 0xFFFFFFFF # macro
|
|
MP1_EXT_SCRATCH4__DATA__SHIFT = 0x0 # macro
|
|
MP1_EXT_SCRATCH4__DATA_MASK = 0xFFFFFFFF # macro
|
|
MP1_EXT_SCRATCH5__DATA__SHIFT = 0x0 # macro
|
|
MP1_EXT_SCRATCH5__DATA_MASK = 0xFFFFFFFF # macro
|
|
MP1_EXT_SCRATCH6__DATA__SHIFT = 0x0 # macro
|
|
MP1_EXT_SCRATCH6__DATA_MASK = 0xFFFFFFFF # macro
|
|
MP1_EXT_SCRATCH7__DATA__SHIFT = 0x0 # macro
|
|
MP1_EXT_SCRATCH7__DATA_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_32__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_32__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_33__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_33__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_34__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_34__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_35__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_35__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_36__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_36__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_37__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_37__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_38__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_38__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_39__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_39__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_40__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_40__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_41__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_41__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_42__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_42__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_43__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_43__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_44__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_44__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_45__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_45__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_46__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_46__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_47__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_47__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_48__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_48__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_49__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_49__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_50__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_50__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_51__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_51__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_52__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_52__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_53__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_53__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_54__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_54__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_55__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_55__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_56__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_56__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_57__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_57__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_58__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_58__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_59__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_59__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_60__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_60__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_61__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_61__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_62__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_62__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_63__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_63__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_64__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_64__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_65__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_65__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_66__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_66__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_67__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_67__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_68__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_68__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_69__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_69__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_70__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_70__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_71__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_71__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_72__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_72__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_73__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_73__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_74__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_74__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_75__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_75__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_76__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_76__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_77__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_77__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_78__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_78__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_79__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_79__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_80__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_80__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_81__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_81__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_82__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_82__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_83__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_83__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_84__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_84__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_85__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_85__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_86__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_86__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_87__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_87__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_88__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_88__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_89__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_89__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_90__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_90__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_91__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_91__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_92__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_92__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_93__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_93__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_94__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_94__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_95__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_95__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_96__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_96__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_97__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_97__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_98__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_98__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_99__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_99__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_100__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_100__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_101__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_101__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_102__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_102__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_C2PMSG_103__CONTENT__SHIFT = 0x0 # macro
|
|
MP1_SMN_C2PMSG_103__CONTENT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_ACTIVE_FCN_ID__VFID__SHIFT = 0x0 # macro
|
|
MP1_SMN_ACTIVE_FCN_ID__VF__SHIFT = 0x1f # macro
|
|
MP1_SMN_ACTIVE_FCN_ID__VFID_MASK = 0x0000001F # macro
|
|
MP1_SMN_ACTIVE_FCN_ID__VF_MASK = 0x80000000 # macro
|
|
MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT = 0x0 # macro
|
|
MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT = 0x10 # macro
|
|
MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK = 0x00000003 # macro
|
|
MP1_SMN_IH_CREDIT__CLIENT_ID_MASK = 0x00FF0000 # macro
|
|
MP1_SMN_IH_SW_INT__ID__SHIFT = 0x0 # macro
|
|
MP1_SMN_IH_SW_INT__VALID__SHIFT = 0x8 # macro
|
|
MP1_SMN_IH_SW_INT__ID_MASK = 0x000000FF # macro
|
|
MP1_SMN_IH_SW_INT__VALID_MASK = 0x00000100 # macro
|
|
MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT = 0x0 # macro
|
|
MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT = 0x8 # macro
|
|
MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK = 0x00000001 # macro
|
|
MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK = 0x00000100 # macro
|
|
MP1_SMN_FPS_CNT__COUNT__SHIFT = 0x0 # macro
|
|
MP1_SMN_FPS_CNT__COUNT_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_PUB_CTRL__RESET__SHIFT = 0x0 # macro
|
|
MP1_SMN_PUB_CTRL__RESET_MASK = 0x00000001 # macro
|
|
MP1_SMN_EXT_SCRATCH0__DATA__SHIFT = 0x0 # macro
|
|
MP1_SMN_EXT_SCRATCH0__DATA_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_EXT_SCRATCH1__DATA__SHIFT = 0x0 # macro
|
|
MP1_SMN_EXT_SCRATCH1__DATA_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_EXT_SCRATCH2__DATA__SHIFT = 0x0 # macro
|
|
MP1_SMN_EXT_SCRATCH2__DATA_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_EXT_SCRATCH3__DATA__SHIFT = 0x0 # macro
|
|
MP1_SMN_EXT_SCRATCH3__DATA_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_EXT_SCRATCH4__DATA__SHIFT = 0x0 # macro
|
|
MP1_SMN_EXT_SCRATCH4__DATA_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_EXT_SCRATCH5__DATA__SHIFT = 0x0 # macro
|
|
MP1_SMN_EXT_SCRATCH5__DATA_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_EXT_SCRATCH6__DATA__SHIFT = 0x0 # macro
|
|
MP1_SMN_EXT_SCRATCH6__DATA_MASK = 0xFFFFFFFF # macro
|
|
MP1_SMN_EXT_SCRATCH7__DATA__SHIFT = 0x0 # macro
|
|
MP1_SMN_EXT_SCRATCH7__DATA_MASK = 0xFFFFFFFF # macro
|
|
MP1_PMI_3_START__ENABLE_MASK = 0x80000000 # macro
|
|
MP1_PMI_3_FIFO__DEPTH_MASK = 0x00000fff # macro
|
|
MP1_PMI_3_START__ENABLE__SHIFT = 0x0000001f # macro
|
|
MP1_PMI_3_FIFO__DEPTH__SHIFT = 0x00000000 # macro
|
|
__all__ = \
|
|
['MP0_SMN_ACTIVE_FCN_ID__VFID_MASK',
|
|
'MP0_SMN_ACTIVE_FCN_ID__VFID__SHIFT',
|
|
'MP0_SMN_ACTIVE_FCN_ID__VF_MASK',
|
|
'MP0_SMN_ACTIVE_FCN_ID__VF__SHIFT',
|
|
'MP0_SMN_C2PMSG_100__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_100__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_101__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_101__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_102__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_102__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_103__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_103__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_32__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_32__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_33__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_33__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_34__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_34__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_35__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_35__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_36__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_36__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_37__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_37__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_38__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_38__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_39__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_39__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_40__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_40__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_41__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_41__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_42__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_42__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_43__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_43__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_44__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_44__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_45__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_45__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_46__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_46__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_47__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_47__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_48__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_48__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_49__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_49__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_50__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_50__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_51__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_51__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_52__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_52__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_53__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_53__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_54__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_54__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_55__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_55__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_56__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_56__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_57__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_57__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_58__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_58__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_59__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_59__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_60__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_60__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_61__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_61__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_62__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_62__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_63__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_63__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_64__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_64__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_65__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_65__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_66__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_66__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_67__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_67__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_68__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_68__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_69__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_69__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_70__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_70__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_71__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_71__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_72__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_72__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_73__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_73__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_74__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_74__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_75__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_75__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_76__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_76__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_77__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_77__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_78__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_78__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_79__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_79__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_80__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_80__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_81__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_81__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_82__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_82__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_83__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_83__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_84__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_84__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_85__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_85__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_86__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_86__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_87__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_87__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_88__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_88__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_89__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_89__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_90__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_90__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_91__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_91__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_92__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_92__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_93__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_93__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_94__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_94__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_95__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_95__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_96__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_96__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_97__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_97__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_98__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_98__CONTENT__SHIFT',
|
|
'MP0_SMN_C2PMSG_99__CONTENT_MASK',
|
|
'MP0_SMN_C2PMSG_99__CONTENT__SHIFT',
|
|
'MP0_SMN_IH_CREDIT__CLIENT_ID_MASK',
|
|
'MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT',
|
|
'MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK',
|
|
'MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT',
|
|
'MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK',
|
|
'MP0_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT',
|
|
'MP0_SMN_IH_SW_INT_CTRL__INT_MASK_MASK',
|
|
'MP0_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT',
|
|
'MP0_SMN_IH_SW_INT__ID_MASK', 'MP0_SMN_IH_SW_INT__ID__SHIFT',
|
|
'MP0_SMN_IH_SW_INT__VALID_MASK',
|
|
'MP0_SMN_IH_SW_INT__VALID__SHIFT', 'MP1_ACTIVE_FCN_ID__VFID_MASK',
|
|
'MP1_ACTIVE_FCN_ID__VFID__SHIFT', 'MP1_ACTIVE_FCN_ID__VF_MASK',
|
|
'MP1_ACTIVE_FCN_ID__VF__SHIFT', 'MP1_C2PMSG_0__CONTENT_MASK',
|
|
'MP1_C2PMSG_0__CONTENT__SHIFT', 'MP1_C2PMSG_100__CONTENT_MASK',
|
|
'MP1_C2PMSG_100__CONTENT__SHIFT', 'MP1_C2PMSG_101__CONTENT_MASK',
|
|
'MP1_C2PMSG_101__CONTENT__SHIFT', 'MP1_C2PMSG_102__CONTENT_MASK',
|
|
'MP1_C2PMSG_102__CONTENT__SHIFT', 'MP1_C2PMSG_103__CONTENT_MASK',
|
|
'MP1_C2PMSG_103__CONTENT__SHIFT', 'MP1_C2PMSG_10__CONTENT_MASK',
|
|
'MP1_C2PMSG_10__CONTENT__SHIFT', 'MP1_C2PMSG_11__CONTENT_MASK',
|
|
'MP1_C2PMSG_11__CONTENT__SHIFT', 'MP1_C2PMSG_12__CONTENT_MASK',
|
|
'MP1_C2PMSG_12__CONTENT__SHIFT', 'MP1_C2PMSG_13__CONTENT_MASK',
|
|
'MP1_C2PMSG_13__CONTENT__SHIFT', 'MP1_C2PMSG_14__CONTENT_MASK',
|
|
'MP1_C2PMSG_14__CONTENT__SHIFT', 'MP1_C2PMSG_15__CONTENT_MASK',
|
|
'MP1_C2PMSG_15__CONTENT__SHIFT', 'MP1_C2PMSG_16__CONTENT_MASK',
|
|
'MP1_C2PMSG_16__CONTENT__SHIFT', 'MP1_C2PMSG_17__CONTENT_MASK',
|
|
'MP1_C2PMSG_17__CONTENT__SHIFT', 'MP1_C2PMSG_18__CONTENT_MASK',
|
|
'MP1_C2PMSG_18__CONTENT__SHIFT', 'MP1_C2PMSG_19__CONTENT_MASK',
|
|
'MP1_C2PMSG_19__CONTENT__SHIFT', 'MP1_C2PMSG_1__CONTENT_MASK',
|
|
'MP1_C2PMSG_1__CONTENT__SHIFT', 'MP1_C2PMSG_20__CONTENT_MASK',
|
|
'MP1_C2PMSG_20__CONTENT__SHIFT', 'MP1_C2PMSG_21__CONTENT_MASK',
|
|
'MP1_C2PMSG_21__CONTENT__SHIFT', 'MP1_C2PMSG_22__CONTENT_MASK',
|
|
'MP1_C2PMSG_22__CONTENT__SHIFT', 'MP1_C2PMSG_23__CONTENT_MASK',
|
|
'MP1_C2PMSG_23__CONTENT__SHIFT', 'MP1_C2PMSG_24__CONTENT_MASK',
|
|
'MP1_C2PMSG_24__CONTENT__SHIFT', 'MP1_C2PMSG_25__CONTENT_MASK',
|
|
'MP1_C2PMSG_25__CONTENT__SHIFT', 'MP1_C2PMSG_26__CONTENT_MASK',
|
|
'MP1_C2PMSG_26__CONTENT__SHIFT', 'MP1_C2PMSG_27__CONTENT_MASK',
|
|
'MP1_C2PMSG_27__CONTENT__SHIFT', 'MP1_C2PMSG_28__CONTENT_MASK',
|
|
'MP1_C2PMSG_28__CONTENT__SHIFT', 'MP1_C2PMSG_29__CONTENT_MASK',
|
|
'MP1_C2PMSG_29__CONTENT__SHIFT', 'MP1_C2PMSG_2__CONTENT_MASK',
|
|
'MP1_C2PMSG_2__CONTENT__SHIFT', 'MP1_C2PMSG_30__CONTENT_MASK',
|
|
'MP1_C2PMSG_30__CONTENT__SHIFT', 'MP1_C2PMSG_31__CONTENT_MASK',
|
|
'MP1_C2PMSG_31__CONTENT__SHIFT', 'MP1_C2PMSG_32__CONTENT_MASK',
|
|
'MP1_C2PMSG_32__CONTENT__SHIFT', 'MP1_C2PMSG_33__CONTENT_MASK',
|
|
'MP1_C2PMSG_33__CONTENT__SHIFT', 'MP1_C2PMSG_34__CONTENT_MASK',
|
|
'MP1_C2PMSG_34__CONTENT__SHIFT', 'MP1_C2PMSG_35__CONTENT_MASK',
|
|
'MP1_C2PMSG_35__CONTENT__SHIFT', 'MP1_C2PMSG_36__CONTENT_MASK',
|
|
'MP1_C2PMSG_36__CONTENT__SHIFT', 'MP1_C2PMSG_37__CONTENT_MASK',
|
|
'MP1_C2PMSG_37__CONTENT__SHIFT', 'MP1_C2PMSG_38__CONTENT_MASK',
|
|
'MP1_C2PMSG_38__CONTENT__SHIFT', 'MP1_C2PMSG_39__CONTENT_MASK',
|
|
'MP1_C2PMSG_39__CONTENT__SHIFT', 'MP1_C2PMSG_3__CONTENT_MASK',
|
|
'MP1_C2PMSG_3__CONTENT__SHIFT', 'MP1_C2PMSG_40__CONTENT_MASK',
|
|
'MP1_C2PMSG_40__CONTENT__SHIFT', 'MP1_C2PMSG_41__CONTENT_MASK',
|
|
'MP1_C2PMSG_41__CONTENT__SHIFT', 'MP1_C2PMSG_42__CONTENT_MASK',
|
|
'MP1_C2PMSG_42__CONTENT__SHIFT', 'MP1_C2PMSG_43__CONTENT_MASK',
|
|
'MP1_C2PMSG_43__CONTENT__SHIFT', 'MP1_C2PMSG_44__CONTENT_MASK',
|
|
'MP1_C2PMSG_44__CONTENT__SHIFT', 'MP1_C2PMSG_45__CONTENT_MASK',
|
|
'MP1_C2PMSG_45__CONTENT__SHIFT', 'MP1_C2PMSG_46__CONTENT_MASK',
|
|
'MP1_C2PMSG_46__CONTENT__SHIFT', 'MP1_C2PMSG_47__CONTENT_MASK',
|
|
'MP1_C2PMSG_47__CONTENT__SHIFT', 'MP1_C2PMSG_48__CONTENT_MASK',
|
|
'MP1_C2PMSG_48__CONTENT__SHIFT', 'MP1_C2PMSG_49__CONTENT_MASK',
|
|
'MP1_C2PMSG_49__CONTENT__SHIFT', 'MP1_C2PMSG_4__CONTENT_MASK',
|
|
'MP1_C2PMSG_4__CONTENT__SHIFT', 'MP1_C2PMSG_50__CONTENT_MASK',
|
|
'MP1_C2PMSG_50__CONTENT__SHIFT', 'MP1_C2PMSG_51__CONTENT_MASK',
|
|
'MP1_C2PMSG_51__CONTENT__SHIFT', 'MP1_C2PMSG_52__CONTENT_MASK',
|
|
'MP1_C2PMSG_52__CONTENT__SHIFT', 'MP1_C2PMSG_53__CONTENT_MASK',
|
|
'MP1_C2PMSG_53__CONTENT__SHIFT', 'MP1_C2PMSG_54__CONTENT_MASK',
|
|
'MP1_C2PMSG_54__CONTENT__SHIFT', 'MP1_C2PMSG_55__CONTENT_MASK',
|
|
'MP1_C2PMSG_55__CONTENT__SHIFT', 'MP1_C2PMSG_56__CONTENT_MASK',
|
|
'MP1_C2PMSG_56__CONTENT__SHIFT', 'MP1_C2PMSG_57__CONTENT_MASK',
|
|
'MP1_C2PMSG_57__CONTENT__SHIFT', 'MP1_C2PMSG_58__CONTENT_MASK',
|
|
'MP1_C2PMSG_58__CONTENT__SHIFT', 'MP1_C2PMSG_59__CONTENT_MASK',
|
|
'MP1_C2PMSG_59__CONTENT__SHIFT', 'MP1_C2PMSG_5__CONTENT_MASK',
|
|
'MP1_C2PMSG_5__CONTENT__SHIFT', 'MP1_C2PMSG_60__CONTENT_MASK',
|
|
'MP1_C2PMSG_60__CONTENT__SHIFT', 'MP1_C2PMSG_61__CONTENT_MASK',
|
|
'MP1_C2PMSG_61__CONTENT__SHIFT', 'MP1_C2PMSG_62__CONTENT_MASK',
|
|
'MP1_C2PMSG_62__CONTENT__SHIFT', 'MP1_C2PMSG_63__CONTENT_MASK',
|
|
'MP1_C2PMSG_63__CONTENT__SHIFT', 'MP1_C2PMSG_64__CONTENT_MASK',
|
|
'MP1_C2PMSG_64__CONTENT__SHIFT', 'MP1_C2PMSG_65__CONTENT_MASK',
|
|
'MP1_C2PMSG_65__CONTENT__SHIFT', 'MP1_C2PMSG_66__CONTENT_MASK',
|
|
'MP1_C2PMSG_66__CONTENT__SHIFT', 'MP1_C2PMSG_67__CONTENT_MASK',
|
|
'MP1_C2PMSG_67__CONTENT__SHIFT', 'MP1_C2PMSG_68__CONTENT_MASK',
|
|
'MP1_C2PMSG_68__CONTENT__SHIFT', 'MP1_C2PMSG_69__CONTENT_MASK',
|
|
'MP1_C2PMSG_69__CONTENT__SHIFT', 'MP1_C2PMSG_6__CONTENT_MASK',
|
|
'MP1_C2PMSG_6__CONTENT__SHIFT', 'MP1_C2PMSG_70__CONTENT_MASK',
|
|
'MP1_C2PMSG_70__CONTENT__SHIFT', 'MP1_C2PMSG_71__CONTENT_MASK',
|
|
'MP1_C2PMSG_71__CONTENT__SHIFT', 'MP1_C2PMSG_72__CONTENT_MASK',
|
|
'MP1_C2PMSG_72__CONTENT__SHIFT', 'MP1_C2PMSG_73__CONTENT_MASK',
|
|
'MP1_C2PMSG_73__CONTENT__SHIFT', 'MP1_C2PMSG_74__CONTENT_MASK',
|
|
'MP1_C2PMSG_74__CONTENT__SHIFT', 'MP1_C2PMSG_75__CONTENT_MASK',
|
|
'MP1_C2PMSG_75__CONTENT__SHIFT', 'MP1_C2PMSG_76__CONTENT_MASK',
|
|
'MP1_C2PMSG_76__CONTENT__SHIFT', 'MP1_C2PMSG_77__CONTENT_MASK',
|
|
'MP1_C2PMSG_77__CONTENT__SHIFT', 'MP1_C2PMSG_78__CONTENT_MASK',
|
|
'MP1_C2PMSG_78__CONTENT__SHIFT', 'MP1_C2PMSG_79__CONTENT_MASK',
|
|
'MP1_C2PMSG_79__CONTENT__SHIFT', 'MP1_C2PMSG_7__CONTENT_MASK',
|
|
'MP1_C2PMSG_7__CONTENT__SHIFT', 'MP1_C2PMSG_80__CONTENT_MASK',
|
|
'MP1_C2PMSG_80__CONTENT__SHIFT', 'MP1_C2PMSG_81__CONTENT_MASK',
|
|
'MP1_C2PMSG_81__CONTENT__SHIFT', 'MP1_C2PMSG_82__CONTENT_MASK',
|
|
'MP1_C2PMSG_82__CONTENT__SHIFT', 'MP1_C2PMSG_83__CONTENT_MASK',
|
|
'MP1_C2PMSG_83__CONTENT__SHIFT', 'MP1_C2PMSG_84__CONTENT_MASK',
|
|
'MP1_C2PMSG_84__CONTENT__SHIFT', 'MP1_C2PMSG_85__CONTENT_MASK',
|
|
'MP1_C2PMSG_85__CONTENT__SHIFT', 'MP1_C2PMSG_86__CONTENT_MASK',
|
|
'MP1_C2PMSG_86__CONTENT__SHIFT', 'MP1_C2PMSG_87__CONTENT_MASK',
|
|
'MP1_C2PMSG_87__CONTENT__SHIFT', 'MP1_C2PMSG_88__CONTENT_MASK',
|
|
'MP1_C2PMSG_88__CONTENT__SHIFT', 'MP1_C2PMSG_89__CONTENT_MASK',
|
|
'MP1_C2PMSG_89__CONTENT__SHIFT', 'MP1_C2PMSG_8__CONTENT_MASK',
|
|
'MP1_C2PMSG_8__CONTENT__SHIFT', 'MP1_C2PMSG_90__CONTENT_MASK',
|
|
'MP1_C2PMSG_90__CONTENT__SHIFT', 'MP1_C2PMSG_91__CONTENT_MASK',
|
|
'MP1_C2PMSG_91__CONTENT__SHIFT', 'MP1_C2PMSG_92__CONTENT_MASK',
|
|
'MP1_C2PMSG_92__CONTENT__SHIFT', 'MP1_C2PMSG_93__CONTENT_MASK',
|
|
'MP1_C2PMSG_93__CONTENT__SHIFT', 'MP1_C2PMSG_94__CONTENT_MASK',
|
|
'MP1_C2PMSG_94__CONTENT__SHIFT', 'MP1_C2PMSG_95__CONTENT_MASK',
|
|
'MP1_C2PMSG_95__CONTENT__SHIFT', 'MP1_C2PMSG_96__CONTENT_MASK',
|
|
'MP1_C2PMSG_96__CONTENT__SHIFT', 'MP1_C2PMSG_97__CONTENT_MASK',
|
|
'MP1_C2PMSG_97__CONTENT__SHIFT', 'MP1_C2PMSG_98__CONTENT_MASK',
|
|
'MP1_C2PMSG_98__CONTENT__SHIFT', 'MP1_C2PMSG_99__CONTENT_MASK',
|
|
'MP1_C2PMSG_99__CONTENT__SHIFT', 'MP1_C2PMSG_9__CONTENT_MASK',
|
|
'MP1_C2PMSG_9__CONTENT__SHIFT', 'MP1_EXT_SCRATCH0__DATA_MASK',
|
|
'MP1_EXT_SCRATCH0__DATA__SHIFT', 'MP1_EXT_SCRATCH1__DATA_MASK',
|
|
'MP1_EXT_SCRATCH1__DATA__SHIFT', 'MP1_EXT_SCRATCH2__DATA_MASK',
|
|
'MP1_EXT_SCRATCH2__DATA__SHIFT', 'MP1_EXT_SCRATCH3__DATA_MASK',
|
|
'MP1_EXT_SCRATCH3__DATA__SHIFT', 'MP1_EXT_SCRATCH4__DATA_MASK',
|
|
'MP1_EXT_SCRATCH4__DATA__SHIFT', 'MP1_EXT_SCRATCH5__DATA_MASK',
|
|
'MP1_EXT_SCRATCH5__DATA__SHIFT', 'MP1_EXT_SCRATCH6__DATA_MASK',
|
|
'MP1_EXT_SCRATCH6__DATA__SHIFT', 'MP1_EXT_SCRATCH7__DATA_MASK',
|
|
'MP1_EXT_SCRATCH7__DATA__SHIFT',
|
|
'MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK',
|
|
'MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT',
|
|
'MP1_FIRMWARE_FLAGS__RESERVED_MASK',
|
|
'MP1_FIRMWARE_FLAGS__RESERVED__SHIFT', 'MP1_FPS_CNT__COUNT_MASK',
|
|
'MP1_FPS_CNT__COUNT__SHIFT', 'MP1_IH_CREDIT__CLIENT_ID_MASK',
|
|
'MP1_IH_CREDIT__CLIENT_ID__SHIFT',
|
|
'MP1_IH_CREDIT__CREDIT_VALUE_MASK',
|
|
'MP1_IH_CREDIT__CREDIT_VALUE__SHIFT',
|
|
'MP1_IH_SW_INT_CTRL__INT_ACK_MASK',
|
|
'MP1_IH_SW_INT_CTRL__INT_ACK__SHIFT',
|
|
'MP1_IH_SW_INT_CTRL__INT_MASK_MASK',
|
|
'MP1_IH_SW_INT_CTRL__INT_MASK__SHIFT', 'MP1_IH_SW_INT__ID_MASK',
|
|
'MP1_IH_SW_INT__ID__SHIFT', 'MP1_IH_SW_INT__VALID_MASK',
|
|
'MP1_IH_SW_INT__VALID__SHIFT', 'MP1_P2CMSG_0__CONTENT_MASK',
|
|
'MP1_P2CMSG_0__CONTENT__SHIFT', 'MP1_P2CMSG_1__CONTENT_MASK',
|
|
'MP1_P2CMSG_1__CONTENT__SHIFT', 'MP1_P2CMSG_2__CONTENT_MASK',
|
|
'MP1_P2CMSG_2__CONTENT__SHIFT', 'MP1_P2CMSG_3__CONTENT_MASK',
|
|
'MP1_P2CMSG_3__CONTENT__SHIFT', 'MP1_P2CMSG_INTEN__INTEN_MASK',
|
|
'MP1_P2CMSG_INTEN__INTEN__SHIFT',
|
|
'MP1_P2CMSG_INTSTS__INTSTS0_MASK',
|
|
'MP1_P2CMSG_INTSTS__INTSTS0__SHIFT',
|
|
'MP1_P2CMSG_INTSTS__INTSTS1_MASK',
|
|
'MP1_P2CMSG_INTSTS__INTSTS1__SHIFT',
|
|
'MP1_P2CMSG_INTSTS__INTSTS2_MASK',
|
|
'MP1_P2CMSG_INTSTS__INTSTS2__SHIFT',
|
|
'MP1_P2CMSG_INTSTS__INTSTS3_MASK',
|
|
'MP1_P2CMSG_INTSTS__INTSTS3__SHIFT', 'MP1_P2SMSG_0__CONTENT_MASK',
|
|
'MP1_P2SMSG_0__CONTENT__SHIFT', 'MP1_P2SMSG_1__CONTENT_MASK',
|
|
'MP1_P2SMSG_1__CONTENT__SHIFT', 'MP1_P2SMSG_2__CONTENT_MASK',
|
|
'MP1_P2SMSG_2__CONTENT__SHIFT', 'MP1_P2SMSG_3__CONTENT_MASK',
|
|
'MP1_P2SMSG_3__CONTENT__SHIFT', 'MP1_P2SMSG_INTSTS__INTSTS0_MASK',
|
|
'MP1_P2SMSG_INTSTS__INTSTS0__SHIFT',
|
|
'MP1_P2SMSG_INTSTS__INTSTS1_MASK',
|
|
'MP1_P2SMSG_INTSTS__INTSTS1__SHIFT',
|
|
'MP1_P2SMSG_INTSTS__INTSTS2_MASK',
|
|
'MP1_P2SMSG_INTSTS__INTSTS2__SHIFT',
|
|
'MP1_P2SMSG_INTSTS__INTSTS3_MASK',
|
|
'MP1_P2SMSG_INTSTS__INTSTS3__SHIFT', 'MP1_PMI_3_FIFO__DEPTH_MASK',
|
|
'MP1_PMI_3_FIFO__DEPTH__SHIFT', 'MP1_PMI_3_START__ENABLE_MASK',
|
|
'MP1_PMI_3_START__ENABLE__SHIFT', 'MP1_PUB_CTRL__RESET_MASK',
|
|
'MP1_PUB_CTRL__RESET__SHIFT', 'MP1_PUB_SCRATCH0__DATA_MASK',
|
|
'MP1_PUB_SCRATCH0__DATA__SHIFT', 'MP1_PUB_SCRATCH1__DATA_MASK',
|
|
'MP1_PUB_SCRATCH1__DATA__SHIFT', 'MP1_PUB_SCRATCH2__DATA_MASK',
|
|
'MP1_PUB_SCRATCH2__DATA__SHIFT', 'MP1_PUB_SCRATCH3__DATA_MASK',
|
|
'MP1_PUB_SCRATCH3__DATA__SHIFT', 'MP1_S2PMSG_0__CONTENT_MASK',
|
|
'MP1_S2PMSG_0__CONTENT__SHIFT',
|
|
'MP1_SMN_ACTIVE_FCN_ID__VFID_MASK',
|
|
'MP1_SMN_ACTIVE_FCN_ID__VFID__SHIFT',
|
|
'MP1_SMN_ACTIVE_FCN_ID__VF_MASK',
|
|
'MP1_SMN_ACTIVE_FCN_ID__VF__SHIFT',
|
|
'MP1_SMN_C2PMSG_100__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_100__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_101__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_101__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_102__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_102__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_103__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_103__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_32__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_32__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_33__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_33__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_34__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_34__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_35__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_35__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_36__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_36__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_37__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_37__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_38__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_38__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_39__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_39__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_40__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_40__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_41__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_41__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_42__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_42__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_43__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_43__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_44__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_44__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_45__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_45__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_46__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_46__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_47__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_47__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_48__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_48__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_49__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_49__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_50__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_50__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_51__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_51__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_52__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_52__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_53__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_53__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_54__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_54__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_55__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_55__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_56__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_56__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_57__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_57__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_58__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_58__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_59__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_59__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_60__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_60__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_61__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_61__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_62__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_62__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_63__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_63__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_64__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_64__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_65__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_65__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_66__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_66__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_67__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_67__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_68__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_68__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_69__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_69__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_70__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_70__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_71__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_71__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_72__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_72__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_73__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_73__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_74__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_74__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_75__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_75__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_76__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_76__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_77__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_77__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_78__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_78__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_79__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_79__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_80__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_80__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_81__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_81__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_82__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_82__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_83__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_83__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_84__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_84__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_85__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_85__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_86__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_86__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_87__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_87__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_88__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_88__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_89__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_89__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_90__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_90__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_91__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_91__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_92__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_92__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_93__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_93__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_94__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_94__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_95__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_95__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_96__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_96__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_97__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_97__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_98__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_98__CONTENT__SHIFT',
|
|
'MP1_SMN_C2PMSG_99__CONTENT_MASK',
|
|
'MP1_SMN_C2PMSG_99__CONTENT__SHIFT',
|
|
'MP1_SMN_EXT_SCRATCH0__DATA_MASK',
|
|
'MP1_SMN_EXT_SCRATCH0__DATA__SHIFT',
|
|
'MP1_SMN_EXT_SCRATCH1__DATA_MASK',
|
|
'MP1_SMN_EXT_SCRATCH1__DATA__SHIFT',
|
|
'MP1_SMN_EXT_SCRATCH2__DATA_MASK',
|
|
'MP1_SMN_EXT_SCRATCH2__DATA__SHIFT',
|
|
'MP1_SMN_EXT_SCRATCH3__DATA_MASK',
|
|
'MP1_SMN_EXT_SCRATCH3__DATA__SHIFT',
|
|
'MP1_SMN_EXT_SCRATCH4__DATA_MASK',
|
|
'MP1_SMN_EXT_SCRATCH4__DATA__SHIFT',
|
|
'MP1_SMN_EXT_SCRATCH5__DATA_MASK',
|
|
'MP1_SMN_EXT_SCRATCH5__DATA__SHIFT',
|
|
'MP1_SMN_EXT_SCRATCH6__DATA_MASK',
|
|
'MP1_SMN_EXT_SCRATCH6__DATA__SHIFT',
|
|
'MP1_SMN_EXT_SCRATCH7__DATA_MASK',
|
|
'MP1_SMN_EXT_SCRATCH7__DATA__SHIFT',
|
|
'MP1_SMN_FPS_CNT__COUNT_MASK', 'MP1_SMN_FPS_CNT__COUNT__SHIFT',
|
|
'MP1_SMN_IH_CREDIT__CLIENT_ID_MASK',
|
|
'MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT',
|
|
'MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK',
|
|
'MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT',
|
|
'MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK',
|
|
'MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT',
|
|
'MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK',
|
|
'MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT',
|
|
'MP1_SMN_IH_SW_INT__ID_MASK', 'MP1_SMN_IH_SW_INT__ID__SHIFT',
|
|
'MP1_SMN_IH_SW_INT__VALID_MASK',
|
|
'MP1_SMN_IH_SW_INT__VALID__SHIFT', 'MP1_SMN_PUB_CTRL__RESET_MASK',
|
|
'MP1_SMN_PUB_CTRL__RESET__SHIFT', '_mp_11_0_2_OFFSET_HEADER',
|
|
'_mp_11_0_2_SH_MASK_HEADER', 'mmMP0_SMN_ACTIVE_FCN_ID',
|
|
'mmMP0_SMN_ACTIVE_FCN_ID_BASE_IDX', 'mmMP0_SMN_C2PMSG_100',
|
|
'mmMP0_SMN_C2PMSG_100_BASE_IDX', 'mmMP0_SMN_C2PMSG_101',
|
|
'mmMP0_SMN_C2PMSG_101_BASE_IDX', 'mmMP0_SMN_C2PMSG_102',
|
|
'mmMP0_SMN_C2PMSG_102_BASE_IDX', 'mmMP0_SMN_C2PMSG_103',
|
|
'mmMP0_SMN_C2PMSG_103_BASE_IDX', 'mmMP0_SMN_C2PMSG_32',
|
|
'mmMP0_SMN_C2PMSG_32_BASE_IDX', 'mmMP0_SMN_C2PMSG_33',
|
|
'mmMP0_SMN_C2PMSG_33_BASE_IDX', 'mmMP0_SMN_C2PMSG_34',
|
|
'mmMP0_SMN_C2PMSG_34_BASE_IDX', 'mmMP0_SMN_C2PMSG_35',
|
|
'mmMP0_SMN_C2PMSG_35_BASE_IDX', 'mmMP0_SMN_C2PMSG_36',
|
|
'mmMP0_SMN_C2PMSG_36_BASE_IDX', 'mmMP0_SMN_C2PMSG_37',
|
|
'mmMP0_SMN_C2PMSG_37_BASE_IDX', 'mmMP0_SMN_C2PMSG_38',
|
|
'mmMP0_SMN_C2PMSG_38_BASE_IDX', 'mmMP0_SMN_C2PMSG_39',
|
|
'mmMP0_SMN_C2PMSG_39_BASE_IDX', 'mmMP0_SMN_C2PMSG_40',
|
|
'mmMP0_SMN_C2PMSG_40_BASE_IDX', 'mmMP0_SMN_C2PMSG_41',
|
|
'mmMP0_SMN_C2PMSG_41_BASE_IDX', 'mmMP0_SMN_C2PMSG_42',
|
|
'mmMP0_SMN_C2PMSG_42_BASE_IDX', 'mmMP0_SMN_C2PMSG_43',
|
|
'mmMP0_SMN_C2PMSG_43_BASE_IDX', 'mmMP0_SMN_C2PMSG_44',
|
|
'mmMP0_SMN_C2PMSG_44_BASE_IDX', 'mmMP0_SMN_C2PMSG_45',
|
|
'mmMP0_SMN_C2PMSG_45_BASE_IDX', 'mmMP0_SMN_C2PMSG_46',
|
|
'mmMP0_SMN_C2PMSG_46_BASE_IDX', 'mmMP0_SMN_C2PMSG_47',
|
|
'mmMP0_SMN_C2PMSG_47_BASE_IDX', 'mmMP0_SMN_C2PMSG_48',
|
|
'mmMP0_SMN_C2PMSG_48_BASE_IDX', 'mmMP0_SMN_C2PMSG_49',
|
|
'mmMP0_SMN_C2PMSG_49_BASE_IDX', 'mmMP0_SMN_C2PMSG_50',
|
|
'mmMP0_SMN_C2PMSG_50_BASE_IDX', 'mmMP0_SMN_C2PMSG_51',
|
|
'mmMP0_SMN_C2PMSG_51_BASE_IDX', 'mmMP0_SMN_C2PMSG_52',
|
|
'mmMP0_SMN_C2PMSG_52_BASE_IDX', 'mmMP0_SMN_C2PMSG_53',
|
|
'mmMP0_SMN_C2PMSG_53_BASE_IDX', 'mmMP0_SMN_C2PMSG_54',
|
|
'mmMP0_SMN_C2PMSG_54_BASE_IDX', 'mmMP0_SMN_C2PMSG_55',
|
|
'mmMP0_SMN_C2PMSG_55_BASE_IDX', 'mmMP0_SMN_C2PMSG_56',
|
|
'mmMP0_SMN_C2PMSG_56_BASE_IDX', 'mmMP0_SMN_C2PMSG_57',
|
|
'mmMP0_SMN_C2PMSG_57_BASE_IDX', 'mmMP0_SMN_C2PMSG_58',
|
|
'mmMP0_SMN_C2PMSG_58_BASE_IDX', 'mmMP0_SMN_C2PMSG_59',
|
|
'mmMP0_SMN_C2PMSG_59_BASE_IDX', 'mmMP0_SMN_C2PMSG_60',
|
|
'mmMP0_SMN_C2PMSG_60_BASE_IDX', 'mmMP0_SMN_C2PMSG_61',
|
|
'mmMP0_SMN_C2PMSG_61_BASE_IDX', 'mmMP0_SMN_C2PMSG_62',
|
|
'mmMP0_SMN_C2PMSG_62_BASE_IDX', 'mmMP0_SMN_C2PMSG_63',
|
|
'mmMP0_SMN_C2PMSG_63_BASE_IDX', 'mmMP0_SMN_C2PMSG_64',
|
|
'mmMP0_SMN_C2PMSG_64_BASE_IDX', 'mmMP0_SMN_C2PMSG_65',
|
|
'mmMP0_SMN_C2PMSG_65_BASE_IDX', 'mmMP0_SMN_C2PMSG_66',
|
|
'mmMP0_SMN_C2PMSG_66_BASE_IDX', 'mmMP0_SMN_C2PMSG_67',
|
|
'mmMP0_SMN_C2PMSG_67_BASE_IDX', 'mmMP0_SMN_C2PMSG_68',
|
|
'mmMP0_SMN_C2PMSG_68_BASE_IDX', 'mmMP0_SMN_C2PMSG_69',
|
|
'mmMP0_SMN_C2PMSG_69_BASE_IDX', 'mmMP0_SMN_C2PMSG_70',
|
|
'mmMP0_SMN_C2PMSG_70_BASE_IDX', 'mmMP0_SMN_C2PMSG_71',
|
|
'mmMP0_SMN_C2PMSG_71_BASE_IDX', 'mmMP0_SMN_C2PMSG_72',
|
|
'mmMP0_SMN_C2PMSG_72_BASE_IDX', 'mmMP0_SMN_C2PMSG_73',
|
|
'mmMP0_SMN_C2PMSG_73_BASE_IDX', 'mmMP0_SMN_C2PMSG_74',
|
|
'mmMP0_SMN_C2PMSG_74_BASE_IDX', 'mmMP0_SMN_C2PMSG_75',
|
|
'mmMP0_SMN_C2PMSG_75_BASE_IDX', 'mmMP0_SMN_C2PMSG_76',
|
|
'mmMP0_SMN_C2PMSG_76_BASE_IDX', 'mmMP0_SMN_C2PMSG_77',
|
|
'mmMP0_SMN_C2PMSG_77_BASE_IDX', 'mmMP0_SMN_C2PMSG_78',
|
|
'mmMP0_SMN_C2PMSG_78_BASE_IDX', 'mmMP0_SMN_C2PMSG_79',
|
|
'mmMP0_SMN_C2PMSG_79_BASE_IDX', 'mmMP0_SMN_C2PMSG_80',
|
|
'mmMP0_SMN_C2PMSG_80_BASE_IDX', 'mmMP0_SMN_C2PMSG_81',
|
|
'mmMP0_SMN_C2PMSG_81_BASE_IDX', 'mmMP0_SMN_C2PMSG_82',
|
|
'mmMP0_SMN_C2PMSG_82_BASE_IDX', 'mmMP0_SMN_C2PMSG_83',
|
|
'mmMP0_SMN_C2PMSG_83_BASE_IDX', 'mmMP0_SMN_C2PMSG_84',
|
|
'mmMP0_SMN_C2PMSG_84_BASE_IDX', 'mmMP0_SMN_C2PMSG_85',
|
|
'mmMP0_SMN_C2PMSG_85_BASE_IDX', 'mmMP0_SMN_C2PMSG_86',
|
|
'mmMP0_SMN_C2PMSG_86_BASE_IDX', 'mmMP0_SMN_C2PMSG_87',
|
|
'mmMP0_SMN_C2PMSG_87_BASE_IDX', 'mmMP0_SMN_C2PMSG_88',
|
|
'mmMP0_SMN_C2PMSG_88_BASE_IDX', 'mmMP0_SMN_C2PMSG_89',
|
|
'mmMP0_SMN_C2PMSG_89_BASE_IDX', 'mmMP0_SMN_C2PMSG_90',
|
|
'mmMP0_SMN_C2PMSG_90_BASE_IDX', 'mmMP0_SMN_C2PMSG_91',
|
|
'mmMP0_SMN_C2PMSG_91_BASE_IDX', 'mmMP0_SMN_C2PMSG_92',
|
|
'mmMP0_SMN_C2PMSG_92_BASE_IDX', 'mmMP0_SMN_C2PMSG_93',
|
|
'mmMP0_SMN_C2PMSG_93_BASE_IDX', 'mmMP0_SMN_C2PMSG_94',
|
|
'mmMP0_SMN_C2PMSG_94_BASE_IDX', 'mmMP0_SMN_C2PMSG_95',
|
|
'mmMP0_SMN_C2PMSG_95_BASE_IDX', 'mmMP0_SMN_C2PMSG_96',
|
|
'mmMP0_SMN_C2PMSG_96_BASE_IDX', 'mmMP0_SMN_C2PMSG_97',
|
|
'mmMP0_SMN_C2PMSG_97_BASE_IDX', 'mmMP0_SMN_C2PMSG_98',
|
|
'mmMP0_SMN_C2PMSG_98_BASE_IDX', 'mmMP0_SMN_C2PMSG_99',
|
|
'mmMP0_SMN_C2PMSG_99_BASE_IDX', 'mmMP0_SMN_IH_CREDIT',
|
|
'mmMP0_SMN_IH_CREDIT_BASE_IDX', 'mmMP0_SMN_IH_SW_INT',
|
|
'mmMP0_SMN_IH_SW_INT_BASE_IDX', 'mmMP0_SMN_IH_SW_INT_CTRL',
|
|
'mmMP0_SMN_IH_SW_INT_CTRL_BASE_IDX', 'mmMP1_SMN_ACTIVE_FCN_ID',
|
|
'mmMP1_SMN_ACTIVE_FCN_ID_BASE_IDX', 'mmMP1_SMN_C2PMSG_100',
|
|
'mmMP1_SMN_C2PMSG_100_BASE_IDX', 'mmMP1_SMN_C2PMSG_101',
|
|
'mmMP1_SMN_C2PMSG_101_BASE_IDX', 'mmMP1_SMN_C2PMSG_102',
|
|
'mmMP1_SMN_C2PMSG_102_BASE_IDX', 'mmMP1_SMN_C2PMSG_103',
|
|
'mmMP1_SMN_C2PMSG_103_BASE_IDX', 'mmMP1_SMN_C2PMSG_32',
|
|
'mmMP1_SMN_C2PMSG_32_BASE_IDX', 'mmMP1_SMN_C2PMSG_33',
|
|
'mmMP1_SMN_C2PMSG_33_BASE_IDX', 'mmMP1_SMN_C2PMSG_34',
|
|
'mmMP1_SMN_C2PMSG_34_BASE_IDX', 'mmMP1_SMN_C2PMSG_35',
|
|
'mmMP1_SMN_C2PMSG_35_BASE_IDX', 'mmMP1_SMN_C2PMSG_36',
|
|
'mmMP1_SMN_C2PMSG_36_BASE_IDX', 'mmMP1_SMN_C2PMSG_37',
|
|
'mmMP1_SMN_C2PMSG_37_BASE_IDX', 'mmMP1_SMN_C2PMSG_38',
|
|
'mmMP1_SMN_C2PMSG_38_BASE_IDX', 'mmMP1_SMN_C2PMSG_39',
|
|
'mmMP1_SMN_C2PMSG_39_BASE_IDX', 'mmMP1_SMN_C2PMSG_40',
|
|
'mmMP1_SMN_C2PMSG_40_BASE_IDX', 'mmMP1_SMN_C2PMSG_41',
|
|
'mmMP1_SMN_C2PMSG_41_BASE_IDX', 'mmMP1_SMN_C2PMSG_42',
|
|
'mmMP1_SMN_C2PMSG_42_BASE_IDX', 'mmMP1_SMN_C2PMSG_43',
|
|
'mmMP1_SMN_C2PMSG_43_BASE_IDX', 'mmMP1_SMN_C2PMSG_44',
|
|
'mmMP1_SMN_C2PMSG_44_BASE_IDX', 'mmMP1_SMN_C2PMSG_45',
|
|
'mmMP1_SMN_C2PMSG_45_BASE_IDX', 'mmMP1_SMN_C2PMSG_46',
|
|
'mmMP1_SMN_C2PMSG_46_BASE_IDX', 'mmMP1_SMN_C2PMSG_47',
|
|
'mmMP1_SMN_C2PMSG_47_BASE_IDX', 'mmMP1_SMN_C2PMSG_48',
|
|
'mmMP1_SMN_C2PMSG_48_BASE_IDX', 'mmMP1_SMN_C2PMSG_49',
|
|
'mmMP1_SMN_C2PMSG_49_BASE_IDX', 'mmMP1_SMN_C2PMSG_50',
|
|
'mmMP1_SMN_C2PMSG_50_BASE_IDX', 'mmMP1_SMN_C2PMSG_51',
|
|
'mmMP1_SMN_C2PMSG_51_BASE_IDX', 'mmMP1_SMN_C2PMSG_52',
|
|
'mmMP1_SMN_C2PMSG_52_BASE_IDX', 'mmMP1_SMN_C2PMSG_53',
|
|
'mmMP1_SMN_C2PMSG_53_BASE_IDX', 'mmMP1_SMN_C2PMSG_54',
|
|
'mmMP1_SMN_C2PMSG_54_BASE_IDX', 'mmMP1_SMN_C2PMSG_55',
|
|
'mmMP1_SMN_C2PMSG_55_BASE_IDX', 'mmMP1_SMN_C2PMSG_56',
|
|
'mmMP1_SMN_C2PMSG_56_BASE_IDX', 'mmMP1_SMN_C2PMSG_57',
|
|
'mmMP1_SMN_C2PMSG_57_BASE_IDX', 'mmMP1_SMN_C2PMSG_58',
|
|
'mmMP1_SMN_C2PMSG_58_BASE_IDX', 'mmMP1_SMN_C2PMSG_59',
|
|
'mmMP1_SMN_C2PMSG_59_BASE_IDX', 'mmMP1_SMN_C2PMSG_60',
|
|
'mmMP1_SMN_C2PMSG_60_BASE_IDX', 'mmMP1_SMN_C2PMSG_61',
|
|
'mmMP1_SMN_C2PMSG_61_BASE_IDX', 'mmMP1_SMN_C2PMSG_62',
|
|
'mmMP1_SMN_C2PMSG_62_BASE_IDX', 'mmMP1_SMN_C2PMSG_63',
|
|
'mmMP1_SMN_C2PMSG_63_BASE_IDX', 'mmMP1_SMN_C2PMSG_64',
|
|
'mmMP1_SMN_C2PMSG_64_BASE_IDX', 'mmMP1_SMN_C2PMSG_65',
|
|
'mmMP1_SMN_C2PMSG_65_BASE_IDX', 'mmMP1_SMN_C2PMSG_66',
|
|
'mmMP1_SMN_C2PMSG_66_BASE_IDX', 'mmMP1_SMN_C2PMSG_67',
|
|
'mmMP1_SMN_C2PMSG_67_BASE_IDX', 'mmMP1_SMN_C2PMSG_68',
|
|
'mmMP1_SMN_C2PMSG_68_BASE_IDX', 'mmMP1_SMN_C2PMSG_69',
|
|
'mmMP1_SMN_C2PMSG_69_BASE_IDX', 'mmMP1_SMN_C2PMSG_70',
|
|
'mmMP1_SMN_C2PMSG_70_BASE_IDX', 'mmMP1_SMN_C2PMSG_71',
|
|
'mmMP1_SMN_C2PMSG_71_BASE_IDX', 'mmMP1_SMN_C2PMSG_72',
|
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'mmMP1_SMN_C2PMSG_72_BASE_IDX', 'mmMP1_SMN_C2PMSG_73',
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'mmMP1_SMN_C2PMSG_73_BASE_IDX', 'mmMP1_SMN_C2PMSG_74',
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'mmMP1_SMN_C2PMSG_74_BASE_IDX', 'mmMP1_SMN_C2PMSG_75',
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'mmMP1_SMN_C2PMSG_75_BASE_IDX', 'mmMP1_SMN_C2PMSG_76',
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'mmMP1_SMN_C2PMSG_76_BASE_IDX', 'mmMP1_SMN_C2PMSG_77',
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'mmMP1_SMN_C2PMSG_77_BASE_IDX', 'mmMP1_SMN_C2PMSG_78',
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'mmMP1_SMN_C2PMSG_78_BASE_IDX', 'mmMP1_SMN_C2PMSG_79',
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'mmMP1_SMN_C2PMSG_79_BASE_IDX', 'mmMP1_SMN_C2PMSG_80',
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'mmMP1_SMN_C2PMSG_80_BASE_IDX', 'mmMP1_SMN_C2PMSG_81',
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'mmMP1_SMN_C2PMSG_81_BASE_IDX', 'mmMP1_SMN_C2PMSG_82',
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'mmMP1_SMN_C2PMSG_82_BASE_IDX', 'mmMP1_SMN_C2PMSG_83',
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'mmMP1_SMN_C2PMSG_83_BASE_IDX', 'mmMP1_SMN_C2PMSG_84',
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'mmMP1_SMN_C2PMSG_84_BASE_IDX', 'mmMP1_SMN_C2PMSG_85',
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'mmMP1_SMN_C2PMSG_85_BASE_IDX', 'mmMP1_SMN_C2PMSG_86',
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'mmMP1_SMN_C2PMSG_86_BASE_IDX', 'mmMP1_SMN_C2PMSG_87',
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'mmMP1_SMN_C2PMSG_87_BASE_IDX', 'mmMP1_SMN_C2PMSG_88',
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'mmMP1_SMN_C2PMSG_88_BASE_IDX', 'mmMP1_SMN_C2PMSG_89',
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'mmMP1_SMN_C2PMSG_89_BASE_IDX', 'mmMP1_SMN_C2PMSG_90',
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'mmMP1_SMN_C2PMSG_90_BASE_IDX', 'mmMP1_SMN_C2PMSG_91',
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'mmMP1_SMN_C2PMSG_91_BASE_IDX', 'mmMP1_SMN_C2PMSG_92',
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'mmMP1_SMN_C2PMSG_92_BASE_IDX', 'mmMP1_SMN_C2PMSG_93',
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'mmMP1_SMN_C2PMSG_93_BASE_IDX', 'mmMP1_SMN_C2PMSG_94',
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'mmMP1_SMN_C2PMSG_94_BASE_IDX', 'mmMP1_SMN_C2PMSG_95',
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'mmMP1_SMN_C2PMSG_95_BASE_IDX', 'mmMP1_SMN_C2PMSG_96',
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'mmMP1_SMN_C2PMSG_96_BASE_IDX', 'mmMP1_SMN_C2PMSG_97',
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'mmMP1_SMN_C2PMSG_97_BASE_IDX', 'mmMP1_SMN_C2PMSG_98',
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'mmMP1_SMN_C2PMSG_98_BASE_IDX', 'mmMP1_SMN_C2PMSG_99',
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'mmMP1_SMN_C2PMSG_99_BASE_IDX', 'mmMP1_SMN_EXT_SCRATCH0',
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'mmMP1_SMN_EXT_SCRATCH0_BASE_IDX', 'mmMP1_SMN_EXT_SCRATCH1',
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'mmMP1_SMN_EXT_SCRATCH1_BASE_IDX', 'mmMP1_SMN_EXT_SCRATCH2',
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'mmMP1_SMN_EXT_SCRATCH2_BASE_IDX', 'mmMP1_SMN_EXT_SCRATCH3',
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'mmMP1_SMN_EXT_SCRATCH3_BASE_IDX', 'mmMP1_SMN_EXT_SCRATCH4',
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'mmMP1_SMN_EXT_SCRATCH4_BASE_IDX', 'mmMP1_SMN_EXT_SCRATCH5',
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'mmMP1_SMN_EXT_SCRATCH5_BASE_IDX', 'mmMP1_SMN_EXT_SCRATCH6',
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'mmMP1_SMN_EXT_SCRATCH6_BASE_IDX', 'mmMP1_SMN_EXT_SCRATCH7',
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'mmMP1_SMN_EXT_SCRATCH7_BASE_IDX', 'mmMP1_SMN_FPS_CNT',
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'mmMP1_SMN_FPS_CNT_BASE_IDX', 'mmMP1_SMN_IH_CREDIT',
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'mmMP1_SMN_IH_CREDIT_BASE_IDX', 'mmMP1_SMN_IH_SW_INT',
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'mmMP1_SMN_IH_SW_INT_BASE_IDX', 'mmMP1_SMN_IH_SW_INT_CTRL',
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'mmMP1_SMN_IH_SW_INT_CTRL_BASE_IDX', 'mmMP1_SMN_PUB_CTRL',
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'mmMP1_SMN_PUB_CTRL_BASE_IDX', 'smnMP1_PMI_3',
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'smnMP1_PMI_3_FIFO', 'smnMP1_PMI_3_START']
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