568 lines
18 KiB
C
568 lines
18 KiB
C
/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef _DISCOVERY_H_
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#define _DISCOVERY_H_
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#define uint32_t unsigned int
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#define uint8_t unsigned char
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#define uint16_t unsigned short
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#define uint64_t unsigned long long
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#define u32 unsigned int
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#define u8 unsigned char
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#define u16 unsigned short
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#define u64 unsigned long long
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#define bool unsigned char
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#define PSP_HEADER_SIZE 256
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#define BINARY_SIGNATURE 0x28211407
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#define DISCOVERY_TABLE_SIGNATURE 0x53445049
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#define GC_TABLE_ID 0x4347
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#define HARVEST_TABLE_SIGNATURE 0x56524148
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#define VCN_INFO_TABLE_ID 0x004E4356
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#define MALL_INFO_TABLE_ID 0x4C4C414D
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#define NPS_INFO_TABLE_ID 0x0053504E
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typedef enum {
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IP_DISCOVERY = 0,
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GC,
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HARVEST_INFO,
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VCN_INFO,
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MALL_INFO,
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NPS_INFO,
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TOTAL_TABLES = 6
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} table;
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#pragma pack(1)
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typedef struct table_info
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{
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uint16_t offset; /* Byte offset */
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uint16_t checksum; /* Byte sum of the table */
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uint16_t size; /* Table size */
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uint16_t padding;
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} table_info;
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typedef struct binary_header
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{
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/* psp structure should go at the top of this structure */
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uint32_t binary_signature; /* 0x7, 0x14, 0x21, 0x28 */
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uint16_t version_major;
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uint16_t version_minor;
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uint16_t binary_checksum; /* Byte sum of the binary after this field */
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uint16_t binary_size; /* Binary Size*/
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table_info table_list[TOTAL_TABLES];
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} binary_header;
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typedef struct die_info
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{
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uint16_t die_id;
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uint16_t die_offset; /* Points to the corresponding die_header structure */
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} die_info;
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typedef struct ip_discovery_header
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{
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uint32_t signature; /* Table Signature */
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uint16_t version; /* Table Version */
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uint16_t size; /* Table Size */
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uint32_t id; /* Table ID */
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uint16_t num_dies; /* Number of Dies */
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die_info die_info[16]; /* list die information for up to 16 dies */
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union {
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uint16_t padding[1]; /* version <= 3 */
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struct { /* version == 4 */
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uint8_t base_addr_64_bit : 1; /* ip structures are using 64 bit base address */
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uint8_t reserved : 7;
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uint8_t reserved2;
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};
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};
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} ip_discovery_header;
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typedef struct ip
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{
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uint16_t hw_id; /* Hardware ID */
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uint8_t number_instance; /* instance of the IP */
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uint8_t num_base_address; /* Number of Base Addresses */
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uint8_t major; /* HCID Major */
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uint8_t minor; /* HCID Minor */
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uint8_t revision; /* HCID Revision */
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#if defined(__BIG_ENDIAN)
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uint8_t reserved : 4; /* Placeholder field */
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uint8_t harvest : 4; /* Harvest */
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#else
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uint8_t harvest : 4; /* Harvest */
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uint8_t reserved : 4; /* Placeholder field */
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#endif
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uint32_t base_address[1]; /* variable number of Addresses */
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} ip;
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typedef struct ip_v3
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{
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uint16_t hw_id; /* Hardware ID */
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uint8_t instance_number; /* Instance number for the IP */
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uint8_t num_base_address; /* Number of base addresses*/
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uint8_t major; /* Hardware ID.major version */
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uint8_t minor; /* Hardware ID.minor version */
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uint8_t revision; /* Hardware ID.revision version */
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#if defined(__BIG_ENDIAN)
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uint8_t variant : 4; /* HW variant */
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uint8_t sub_revision : 4; /* HCID Sub-Revision */
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#else
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uint8_t sub_revision : 4; /* HCID Sub-Revision */
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uint8_t variant : 4; /* HW variant */
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#endif
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uint32_t base_address[1]; /* Base Address list. Corresponds to the num_base_address field*/
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} ip_v3;
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typedef struct ip_v4 {
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uint16_t hw_id; /* Hardware ID */
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uint8_t instance_number; /* Instance number for the IP */
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uint8_t num_base_address; /* Number of base addresses*/
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uint8_t major; /* Hardware ID.major version */
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uint8_t minor; /* Hardware ID.minor version */
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uint8_t revision; /* Hardware ID.revision version */
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#if defined(LITTLEENDIAN_CPU)
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uint8_t sub_revision : 4; /* HCID Sub-Revision */
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uint8_t variant : 4; /* HW variant */
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#elif defined(BIGENDIAN_CPU)
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uint8_t variant : 4; /* HW variant */
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uint8_t sub_revision : 4; /* HCID Sub-Revision */
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#endif
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uint64_t base_address_64[1];
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} ip_v4;
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typedef struct die_header
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{
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uint16_t die_id;
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uint16_t num_ips;
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} die_header;
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typedef struct ip_structure
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{
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ip_discovery_header* header;
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struct die
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{
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die_header *die_header;
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union
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{
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ip *ip_list;
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ip_v3 *ip_v3_list;
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ip_v4 *ip_v4_list;
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}; /* IP list. Variable size*/
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} die;
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} ip_structure;
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struct gpu_info_header {
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uint32_t table_id; /* table ID */
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uint16_t version_major; /* table version */
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uint16_t version_minor; /* table version */
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uint32_t size; /* size of the entire header+data in bytes */
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};
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struct gc_info_v1_0 {
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struct gpu_info_header header;
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uint32_t gc_num_se;
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uint32_t gc_num_wgp0_per_sa;
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uint32_t gc_num_wgp1_per_sa;
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uint32_t gc_num_rb_per_se;
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uint32_t gc_num_gl2c;
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uint32_t gc_num_gprs;
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uint32_t gc_num_max_gs_thds;
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uint32_t gc_gs_table_depth;
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uint32_t gc_gsprim_buff_depth;
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uint32_t gc_parameter_cache_depth;
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uint32_t gc_double_offchip_lds_buffer;
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uint32_t gc_wave_size;
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uint32_t gc_max_waves_per_simd;
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uint32_t gc_max_scratch_slots_per_cu;
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uint32_t gc_lds_size;
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uint32_t gc_num_sc_per_se;
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uint32_t gc_num_sa_per_se;
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uint32_t gc_num_packer_per_sc;
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uint32_t gc_num_gl2a;
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};
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struct gc_info_v1_1 {
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struct gpu_info_header header;
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uint32_t gc_num_se;
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uint32_t gc_num_wgp0_per_sa;
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uint32_t gc_num_wgp1_per_sa;
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uint32_t gc_num_rb_per_se;
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uint32_t gc_num_gl2c;
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uint32_t gc_num_gprs;
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uint32_t gc_num_max_gs_thds;
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uint32_t gc_gs_table_depth;
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uint32_t gc_gsprim_buff_depth;
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uint32_t gc_parameter_cache_depth;
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uint32_t gc_double_offchip_lds_buffer;
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uint32_t gc_wave_size;
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uint32_t gc_max_waves_per_simd;
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uint32_t gc_max_scratch_slots_per_cu;
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uint32_t gc_lds_size;
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uint32_t gc_num_sc_per_se;
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uint32_t gc_num_sa_per_se;
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uint32_t gc_num_packer_per_sc;
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uint32_t gc_num_gl2a;
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uint32_t gc_num_tcp_per_sa;
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uint32_t gc_num_sdp_interface;
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uint32_t gc_num_tcps;
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};
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struct gc_info_v1_2 {
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struct gpu_info_header header;
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uint32_t gc_num_se;
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uint32_t gc_num_wgp0_per_sa;
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uint32_t gc_num_wgp1_per_sa;
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uint32_t gc_num_rb_per_se;
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uint32_t gc_num_gl2c;
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uint32_t gc_num_gprs;
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uint32_t gc_num_max_gs_thds;
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uint32_t gc_gs_table_depth;
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uint32_t gc_gsprim_buff_depth;
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uint32_t gc_parameter_cache_depth;
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uint32_t gc_double_offchip_lds_buffer;
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uint32_t gc_wave_size;
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uint32_t gc_max_waves_per_simd;
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uint32_t gc_max_scratch_slots_per_cu;
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uint32_t gc_lds_size;
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uint32_t gc_num_sc_per_se;
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uint32_t gc_num_sa_per_se;
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uint32_t gc_num_packer_per_sc;
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uint32_t gc_num_gl2a;
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uint32_t gc_num_tcp_per_sa;
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uint32_t gc_num_sdp_interface;
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uint32_t gc_num_tcps;
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uint32_t gc_num_tcp_per_wpg;
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uint32_t gc_tcp_l1_size;
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uint32_t gc_num_sqc_per_wgp;
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uint32_t gc_l1_instruction_cache_size_per_sqc;
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uint32_t gc_l1_data_cache_size_per_sqc;
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uint32_t gc_gl1c_per_sa;
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uint32_t gc_gl1c_size_per_instance;
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uint32_t gc_gl2c_per_gpu;
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};
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struct gc_info_v2_0 {
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struct gpu_info_header header;
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uint32_t gc_num_se;
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uint32_t gc_num_cu_per_sh;
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uint32_t gc_num_sh_per_se;
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uint32_t gc_num_rb_per_se;
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uint32_t gc_num_tccs;
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uint32_t gc_num_gprs;
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uint32_t gc_num_max_gs_thds;
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uint32_t gc_gs_table_depth;
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uint32_t gc_gsprim_buff_depth;
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uint32_t gc_parameter_cache_depth;
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uint32_t gc_double_offchip_lds_buffer;
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uint32_t gc_wave_size;
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uint32_t gc_max_waves_per_simd;
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uint32_t gc_max_scratch_slots_per_cu;
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uint32_t gc_lds_size;
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uint32_t gc_num_sc_per_se;
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uint32_t gc_num_packer_per_sc;
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};
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struct gc_info_v2_1 {
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struct gpu_info_header header;
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uint32_t gc_num_se;
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uint32_t gc_num_cu_per_sh;
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uint32_t gc_num_sh_per_se;
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uint32_t gc_num_rb_per_se;
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uint32_t gc_num_tccs;
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uint32_t gc_num_gprs;
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uint32_t gc_num_max_gs_thds;
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uint32_t gc_gs_table_depth;
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uint32_t gc_gsprim_buff_depth;
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uint32_t gc_parameter_cache_depth;
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uint32_t gc_double_offchip_lds_buffer;
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uint32_t gc_wave_size;
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uint32_t gc_max_waves_per_simd;
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uint32_t gc_max_scratch_slots_per_cu;
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uint32_t gc_lds_size;
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uint32_t gc_num_sc_per_se;
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uint32_t gc_num_packer_per_sc;
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/* new for v2_1 */
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uint32_t gc_num_tcp_per_sh;
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uint32_t gc_tcp_size_per_cu;
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uint32_t gc_num_sdp_interface;
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uint32_t gc_num_cu_per_sqc;
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uint32_t gc_instruction_cache_size_per_sqc;
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uint32_t gc_scalar_data_cache_size_per_sqc;
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uint32_t gc_tcc_size;
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};
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typedef struct harvest_info_header {
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uint32_t signature; /* Table Signature */
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uint32_t version; /* Table Version */
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} harvest_info_header;
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typedef struct harvest_info {
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uint16_t hw_id; /* Hardware ID */
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uint8_t number_instance; /* Instance of the IP */
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uint8_t reserved; /* Reserved for alignment */
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} harvest_info;
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typedef struct harvest_table {
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harvest_info_header header;
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harvest_info list[32];
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} harvest_table;
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struct mall_info_header {
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uint32_t table_id; /* table ID */
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uint16_t version_major; /* table version */
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uint16_t version_minor; /* table version */
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uint32_t size_bytes; /* size of the entire header+data in bytes */
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};
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struct mall_info_v1_0 {
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struct mall_info_header header;
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uint32_t mall_size_per_m;
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uint32_t m_s_present;
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uint32_t m_half_use;
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uint32_t m_mall_config;
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uint32_t reserved[5];
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};
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struct mall_info_v2_0 {
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struct mall_info_header header;
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uint32_t mall_size_per_umc;
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uint32_t reserved[8];
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};
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#define VCN_INFO_TABLE_MAX_NUM_INSTANCES 4
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struct vcn_info_header {
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uint32_t table_id; /* table ID */
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uint16_t version_major; /* table version */
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uint16_t version_minor; /* table version */
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uint32_t size_bytes; /* size of the entire header+data in bytes */
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};
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struct vcn_instance_info_v1_0
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{
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uint32_t instance_num; /* VCN IP instance number. 0 - VCN0; 1 - VCN1 etc*/
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union _fuse_data {
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struct {
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uint32_t av1_disabled : 1;
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uint32_t vp9_disabled : 1;
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uint32_t hevc_disabled : 1;
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uint32_t h264_disabled : 1;
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uint32_t reserved : 28;
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} bits;
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uint32_t all_bits;
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} fuse_data;
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uint32_t reserved[2];
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};
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struct vcn_info_v1_0 {
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struct vcn_info_header header;
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uint32_t num_of_instances; /* number of entries used in instance_info below*/
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struct vcn_instance_info_v1_0 instance_info[VCN_INFO_TABLE_MAX_NUM_INSTANCES];
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uint32_t reserved[4];
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};
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#define NPS_INFO_TABLE_MAX_NUM_INSTANCES 12
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struct nps_info_header {
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uint32_t table_id; /* table ID */
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uint16_t version_major; /* table version */
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uint16_t version_minor; /* table version */
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uint32_t size_bytes; /* size of the entire header+data in bytes = 0x000000D4 (212) */
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};
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struct nps_instance_info_v1_0 {
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uint64_t base_address;
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uint64_t limit_address;
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};
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struct nps_info_v1_0 {
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struct nps_info_header header;
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uint32_t nps_type;
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uint32_t count;
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struct nps_instance_info_v1_0
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instance_info[NPS_INFO_TABLE_MAX_NUM_INSTANCES];
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};
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enum amd_hw_ip_block_type {
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GC_HWIP = 1,
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HDP_HWIP,
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SDMA0_HWIP,
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SDMA1_HWIP,
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SDMA2_HWIP,
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SDMA3_HWIP,
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SDMA4_HWIP,
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SDMA5_HWIP,
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SDMA6_HWIP,
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SDMA7_HWIP,
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LSDMA_HWIP,
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MMHUB_HWIP,
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ATHUB_HWIP,
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NBIO_HWIP,
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MP0_HWIP,
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MP1_HWIP,
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UVD_HWIP,
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VCN_HWIP = UVD_HWIP,
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JPEG_HWIP = VCN_HWIP,
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VCN1_HWIP,
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VCE_HWIP,
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VPE_HWIP,
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DF_HWIP,
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DCE_HWIP,
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OSSSYS_HWIP,
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SMUIO_HWIP,
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PWR_HWIP,
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NBIF_HWIP,
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THM_HWIP,
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CLK_HWIP,
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UMC_HWIP,
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RSMU_HWIP,
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XGMI_HWIP,
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DCI_HWIP,
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PCIE_HWIP,
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ISP_HWIP,
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MAX_HWIP
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};
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#define HWIP_MAX_INSTANCE 44
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#define HW_ID_MAX 300
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// HW ID
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#define MP1_HWID 1
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#define MP2_HWID 2
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#define THM_HWID 3
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#define SMUIO_HWID 4
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#define FUSE_HWID 5
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#define CLKA_HWID 6
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#define PWR_HWID 10
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#define GC_HWID 11
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#define UVD_HWID 12
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#define VCN_HWID UVD_HWID
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#define AUDIO_AZ_HWID 13
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#define ACP_HWID 14
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#define DCI_HWID 15
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#define DMU_HWID 271
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#define DCO_HWID 16
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#define DIO_HWID 272
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#define XDMA_HWID 17
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#define DCEAZ_HWID 18
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#define DAZ_HWID 274
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#define SDPMUX_HWID 19
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#define NTB_HWID 20
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#define VPE_HWID 21
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#define IOHC_HWID 24
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#define L2IMU_HWID 28
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#define VCE_HWID 32
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#define MMHUB_HWID 34
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#define ATHUB_HWID 35
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#define DBGU_NBIO_HWID 36
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#define DFX_HWID 37
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#define DBGU0_HWID 38
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#define DBGU1_HWID 39
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#define OSSSYS_HWID 40
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#define HDP_HWID 41
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#define SDMA0_HWID 42
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#define SDMA1_HWID 43
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#define ISP_HWID 44
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#define DBGU_IO_HWID 45
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#define DF_HWID 46
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#define CLKB_HWID 47
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#define FCH_HWID 48
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#define DFX_DAP_HWID 49
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#define L1IMU_PCIE_HWID 50
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#define L1IMU_NBIF_HWID 51
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#define L1IMU_IOAGR_HWID 52
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#define L1IMU3_HWID 53
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#define L1IMU4_HWID 54
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#define L1IMU5_HWID 55
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#define L1IMU6_HWID 56
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#define L1IMU7_HWID 57
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#define L1IMU8_HWID 58
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#define L1IMU9_HWID 59
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#define L1IMU10_HWID 60
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#define L1IMU11_HWID 61
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#define L1IMU12_HWID 62
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#define L1IMU13_HWID 63
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#define L1IMU14_HWID 64
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#define L1IMU15_HWID 65
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#define WAFLC_HWID 66
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#define FCH_USB_PD_HWID 67
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#define SDMA2_HWID 68
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#define SDMA3_HWID 69
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#define PCIE_HWID 70
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#define PCS_HWID 80
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#define DDCL_HWID 89
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#define SST_HWID 90
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#define LSDMA_HWID 91
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#define IOAGR_HWID 100
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#define NBIF_HWID 108
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#define IOAPIC_HWID 124
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#define SYSTEMHUB_HWID 128
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#define NTBCCP_HWID 144
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#define UMC_HWID 150
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#define SATA_HWID 168
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#define USB_HWID 170
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|
#define CCXSEC_HWID 176
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#define XGMI_HWID 200
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#define XGBE_HWID 216
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#define MP0_HWID 255
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static int hw_id_map[MAX_HWIP] = {
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[GC_HWIP] = GC_HWID,
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[HDP_HWIP] = HDP_HWID,
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[SDMA0_HWIP] = SDMA0_HWID,
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[SDMA1_HWIP] = SDMA1_HWID,
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[SDMA2_HWIP] = SDMA2_HWID,
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[SDMA3_HWIP] = SDMA3_HWID,
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[LSDMA_HWIP] = LSDMA_HWID,
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[MMHUB_HWIP] = MMHUB_HWID,
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[ATHUB_HWIP] = ATHUB_HWID,
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[NBIO_HWIP] = NBIF_HWID,
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[MP0_HWIP] = MP0_HWID,
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[MP1_HWIP] = MP1_HWID,
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[UVD_HWIP] = UVD_HWID,
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[VCE_HWIP] = VCE_HWID,
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[DF_HWIP] = DF_HWID,
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[DCE_HWIP] = DMU_HWID,
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[OSSSYS_HWIP] = OSSSYS_HWID,
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[SMUIO_HWIP] = SMUIO_HWID,
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[PWR_HWIP] = PWR_HWID,
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[NBIF_HWIP] = NBIF_HWID,
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[THM_HWIP] = THM_HWID,
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[CLK_HWIP] = CLKA_HWID,
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[UMC_HWIP] = UMC_HWID,
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[XGMI_HWIP] = XGMI_HWID,
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|
[DCI_HWIP] = DCI_HWID,
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|
[PCIE_HWIP] = PCIE_HWID,
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|
[VPE_HWIP] = VPE_HWID,
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|
[ISP_HWIP] = ISP_HWID,
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};
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#endif
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