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4, 1 ] ], [ "aneRegs.L2.SourceCfg.AliasConvRslt", [ 484, 5, 1 ] ], [ "aneRegs.L2.SourceCfg.DMAFmt", [ 484, 6, 2 ] ], [ "aneRegs.L2.SourceCfg.DMAInterleave", [ 485, 0, 4 ] ], [ "aneRegs.L2.SourceCfg.DMACmpVec", [ 485, 4, 4 ] ], [ "aneRegs.L2.SourceCfg.DMAOffsetCh", [ 486, 0, 3 ] ], [ "aneRegs.L2.SourceCfg.AliasPlanarSrc", [ 486, 4, 1 ] ], [ "aneRegs.L2.SourceCfg.AliasPlanarRslt", [ 486, 6, 1 ] ], [ "aneRegs.L2.SourceBase.Addr", [ 488, 4, 17 ] ], [ "aneRegs.L2.SourceChannelStride.Stride", [ 492, 4, 17 ] ], [ "aneRegs.L2.SourceRowStride.Stride", [ 496, 4, 17 ] ], [ "aneRegs.L2.ResultCfg.ResultType", [ 528, 0, 2 ] ], [ "aneRegs.L2.ResultCfg.L2BfrMode", [ 528, 3, 1 ] ], [ "aneRegs.L2.ResultCfg.AliasConvSrc", [ 528, 4, 1 ] ], [ "aneRegs.L2.ResultCfg.AliasConvRslt", [ 528, 5, 1 ] ], [ "aneRegs.L2.ResultCfg.DMAFmt", [ 528, 6, 2 ] ], [ "aneRegs.L2.ResultCfg.DMAInterleave", [ 529, 0, 4 ] ], [ "aneRegs.L2.ResultCfg.DMACmpVec", [ 529, 4, 4 ] ], [ "aneRegs.L2.ResultCfg.DMAOffsetCh", [ 530, 0, 3 ] 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"aneRegs.TileDMADst.Fmt.MemFmt", [ 625, 4, 2 ] ], [ "aneRegs.TileDMADst.Fmt.OffsetCh", [ 626, 0, 3 ] ], [ "aneRegs.TileDMADst.Fmt.ZeroPadLast", [ 626, 4, 1 ] ], [ "aneRegs.TileDMADst.Fmt.ZeroPadFirst", [ 626, 5, 1 ] ], [ "aneRegs.TileDMADst.Fmt.CmpVecFill", [ 626, 6, 1 ] ], [ "aneRegs.TileDMADst.Fmt.Interleave", [ 627, 0, 4 ] ], [ "aneRegs.TileDMADst.Fmt.CmpVec", [ 627, 4, 4 ] ] ]